Hi,
I'm trying to understand how to determine transistor geometrys for a CMOS inverter ie. operating as a switch.
For example, the cmos inverter shown here:
I'm not sure what the (W/L) ratio of my transistors should be.
From my understanding, when Vin switches from 0v to Vdd (3.3V), the
PMOS will switch off and the NMOS will switch on. For the output to change voltage from 3.3V to 0V, Cload needs to be discharged through the NMOS device. So if Cload is 2pf at 3.3V (Q=CV, so 6.6e-12 Coloumbs) and I want it to discharge in 2ns then the current flow through the NMOS will be 3.3mA (I=Q/t).
As the NMOS Vds is initially 3.3V (before the capacitor discharges), and the Vgs is 3.3V (as the input has switched, but not yet the output), then the transistor is operating in saturation initially (Vds>Vgs-Vt), so I should use device sizes of (W/L) =
2*Id/(K'(Vgs-Vt)^2). But very quickly, the transistor will be operating in the linear region as the capacitor discharges, so Vds drops (so Vds < Vgs-Vt). Then I recalculate (W/L) using the equation for the linear region of operation, and choose the larger (W/L) value of the two.
But in reality, the NMOS begins switching before 3.3V, at around 0.7V, so at that point the Vgs is much lower which affects the saturation equation (ie. calling for a much larger W/L ratio for the NMOS device). Should I then choose W/L values based on the worst case, when the transistor starts switching at 0.7V (so the minimum Vgs value), in order to meet my 2ns switching time? Or do I calculate W/L based on when the maximum current is drawn (when both NMOS and PMOS are on, I believe, although I'm not sure what this maximum current is - 3.3mA?)? I'm very confused.
If anyone can help clear up how I go about sizing transistors for dynamic switching operation (specifically, how I determine the maximum drain current, and what mode the transistor is operating in so that I know which equation to use to calculate (W/L)), I'd be very happy!
Cheers,
Ted