ldo's opamp problem

We'll be polite and not tell you what we think. :-) Not many opamps work with 1.3V supplies, and not many can deliver 100mA, and I can't remember any that can do both at once. Are we to assume this is a "paper" opamp, or one that exists solely in your computer? In which case your design and your simulation model is where you should be looking to check for trouble.

if you were more polite you'd read more carefully. opamp works for LDO so it doesn't give this current but pass devise does so

the opmamp's load is pass device's gate capacity not resistor

LDO = low-dropout regulator. I see, I read the title as Ido, who had an opamp problem. Who was Ido? Who can say. :-)

Also, I once had an employee by the name of Ibo. Well, anyway...

OK, so you've got an opamp driving a MOSFET (implied by the words gate and capacitance), and the supplied power is 1.3 volts. Are we to assume the opamp also runs on 1.3V and the power MOSFET's gate is being driven with about 1.3 volts, even tho it's expected to deliver 100mA? I don't know of any real-world parts that can be used under these conditions. Are these spice-model parts for an IC-design simulation? Tell us about the parts.

To answer your question, at 3.3V the MOSFET's transconductance goes up with current, as expected, and the loop gain increases. But at 1.3V who can say what's happening? I'm surprised the FET can even deliver 100mA with 1.3V gate drive. Is it a p-channel FET? What part is this? One comment I'll make is that very few spice MOSFET models work correctly in the subthreshold region, and most will give you dramatically-incorrect results, with no semblance to proper MOSFET theory or to any bench measurements.

Finally, when you use the word "saturation" in connection with MOSFETs, you need to define your term. Generally that means the FET has a high enough drain-source voltage to be operating in its constant-current region, which of course is the opposite of what we think of for a BJT, opamp output stage, etc., in saturation. The word saturation can have two opposite meanings in your case.

I presume you're having problems with the loop gain and phase (stability) of your LDO as a function of load current AND load capacitance?

This is tricky business. Compensating such loops is an art. I am the artist ;-)

So I only give out this information on a commercial basis.

If you are using PSpice, download the LoopGain part (from my website), as it gives very accurate results. Then you can see where your problems lie.

...Jim Thompson

Now now, Jim, that's no way to talk to a student. Many of us have learned how to stabilize low-drop-out voltage regulators. I did my first micro-power (25uA) high-current (250mA) version using a power MOSFET in 1973, and we made thousands for use in our oceanographic instruments.

Seeing as I made $7K last week fixing just such a problem, do you think I'm going to provide a dissertation here ?:-)

Discrete and I/C versions are different kinds of problems... I don't have any large value capacitors on-chip... thus the art ;-)

...Jim Thompson

I saw your web and method, but i am not taking about compensation and stability.

the problem is with opamp's gain i think, cause for 1mA and vdd=1.3 difference between inputs is smaller than for 100mA but for vdd=3.3 it's exactly reciprocal and don't know why

Were you planning on answering the questions I asked? Let me add to them what the LDO's output voltage is supposed to be (is that 0.8V), so we can know the pass MOSFET's Vds? Look at a MOSFET's characteristic curves. At high drain voltages, above a few volts, in the "saturated" region, the MOSFET's drain current is flat with drain voltage, and the FET has its highest g_m. Higher currents result in higher g_m and hence loop gain. But with low Vds the MOSFET is in its resistive region, with much lower g_m, although the g_m does increase a small amount at higher currents, but not as much as you get even a little ways toward the saturated region.

Applying this to your opamp and LDO, at 1.3V and 100mA the pass transistor is operating in its low g_m resistive region, and so is the opamp's output pulldown transistor (because it's driving the MOSFET's gate at a full 1.3V), so the opamp gain is down as well. Whether this degrades the gain all the way to less than the 1mA loop gain depends on the parameters of your parts. And then there's the probable issue of gross device-model inaccuracy in the subthreshold region, which is probably where you're working. Were you going to tell us anything about your components?

Power mosfet's gate is driven even by lower VGS than 1.3V. This device has huge dimmensions W=50m L=0.5u

yes, i have noticed that. Domain pole also rises with current load.

it's very large PMOS

it works in saturation so Vds is higher than Vgs-Vth

Win thinks that all that exists is discrete type FET modeled at some archaic modeling level (Level=1 or 3).

Level=7 (PSpice) / Level=49 (HSpice) model subthreshold quite nicely.

Too bad the discrete product crowd can't make adequate models.

I have I/C LDO's operating at 100's of mA with VDD as low as 1.8V.

...Jim Thompson

I were :)

Yes it is 0.8V

But with low Vds the

this pass device works in saturation region, and goes to linear during dropout condition (Vin -Vout< dropout voltage) so "Higher currents result in higher g_m and hence loop gain" as you wrote. but as i wrote earlier i checked the gain before power device.

no, i checked simulation results. at 1.3V it works in saturation, has gm=1.13, vgs 922m vds 185m vth=797m for 100mA and gm=23.87m vgs= 641m for 1mA

and the opamp's gain is down with a different reason i think

it's one stage symetrical ota just for now, the gain is 100V/V works with 50uA

i don't have experience in debugging, what should i check?

regards

sorry for that misunderstanding :)

It's a IC design with level 49 models

Start with a URL link to your schematic, or post it on...

alt.binaries.schematics.electronic

...Jim Thompson

jutek wrote: : hello

: let me know if i am wrong or not.

: under stable vdd condition the opamp's gain should change with the load : changes or be stable?

: when i am simulating the LDO i do ac open loop analysis with different : loads. Power supply is 1.3 V : after that i checked the opamp's gain and saw that for 1mA opamp's gain : is higher than for 100mA

: but with 3.3 vdd the situation is reciprocal, the gain is higher for 100mA

: i surely check it after opamp, i know that pass device's gain changes : with load if works in saturation.

: maybe it is related to differencies at the inputs?

: vref is 0.8 and the second input comes from output and the gain would be : stable if output is 0.8 but is not.

: what do you think ?

Ignore what most other people have told you, first of all. They are stuck doing board-level design with BJTs, and/or have no idea what is involved in designing with MOSFETs, let alone modern IC design. The comments about this being a "paper" design show that. ALL Modern IC design is done based upon verification by simulation (unless the design is being re-used, but some simulation is still done in that case) so, in some sense, all modern IC design is "paper" design. Current MOSFET models are actually very well done, even in the subthreshold region.

Regulator design is hardly an art. You just need to understand what you are doing. Sounds to me, based upon the date you provided, that your pass device isn't big enough. To deliver the necessary current, the opamp is pulling its gate so low that something (probably one of your load devices) in the opamp is going out of saturation in your 1.3V case. The load device going into the linear region reduces the output impedance of your first stage, reducing the gain of the opamp.

It's possible (maybe even more likely) that your pass device is going out of sat., but when you said opamp gain, I assumed you were talking about your opamp separate from the pass device, but technically they constitute a 2-stage opamp, so I'm not sure exactly what you were saying.

Stop and think about what you are doing, how your circuit should behave, and then try to reconcile the two.

Good Luck,

Joe

hello

thank you very much for understanding and reply. I have checked 1.3 condition and W=80m L=0.5u is enough to the neither device goes to linear region. If i make it larger it will have much more capacity than already has. The pass device also works in the saturation.

I think, it can be related to low opamp's gain in 1.3V. I check it outside whole LDO circuit and it is 100V/V. Maybe the difference at inputs comes from this low gain?

no, i checked it, pass device works in the saturation, even for high temperature. I said about opamp'sgain, cause i measured it just before pass device. I also checked pass device's gain and it works normally. For now, i don't use any buffer.

good advice :) i thought i knew how it works but the reality is so different :)

are there any groups about IC design?

thanks and regards

When you separately evaluated the opamp's gain, did you do so with the FET's Ciss as a load?

Rail-to-rail output stages are strongly affected by capacitive loads, as you know, and this is especially true at low supply voltages.

No, what it shows is that jutek gave us little clue this was an IC design in his question. Since IC and discrete-MOSFET-using engineers outnumber IC designers by over 100:1 or some such large ratio, as it must be after all, it's natural NOT to assume one is talking about an IC design here on s.e.d., if it's not stated.

Winfield Hill wrote: : wrote... :>

:> Ignore what most other people have told you, first of all. They :> are stuck doing board-level design with BJTs, and/or have no idea :> what is involved in designing with MOSFETs, let alone modern IC :> design. The comments about this being a "paper" design show that.

: No, what it shows is that jutek gave us little clue this was an : IC design in his question. Since IC and discrete-MOSFET-using : engineers outnumber IC designers by over 100:1 or some such large : ratio, as it must be after all, it's natural NOT to assume one is : talking about an IC design here on s.e.d., if it's not stated.

Fair enough. I suppose that I'm guilty of the "Everybody is like me" syndrome.

Joe

you were right, output's devices go into linear region.

in the low vdd and low load current opamp's gain is bigger than for high load current. it's now understood why.

i think it should be the same for higher vdd but it is not. opamp's gain is lower for lower IL than for higher IL. for higher vdd neither device goes to linear, even for higher load current demand. so where does it come from?

regards