Okay. I'll start out by saying that this is *not* a homework problem. I'm trying to recreate some work I did many years ago which I subsequently lost the notes and spreadsheet for.
My ultimate problem is to compute a reasonable estimate of the power dissipated in a termination resistor as used in a typical digital circuit. This is critical in determining an appropriate minimum package size after consideration of derating requirements. My original solution was applicable to both a source termination driving a CMOS capacitive load or an RC termination at an input.
To this end I'm trying to determine the formula for the transient response of an RC circuit when driven by a ramp function up until a specified rise time. The typical textbook analysis only covers the step response which produces an overly pessimistic estimate of power dissipation. I have found some discussion online involving the idealized unit ramp function but the formula presented have been simplified due to the unitless ramp and don't provide any indication on how to incorporate the rise time of the ramp for a real world analysis.
With the voltage across the resistor described for both the ramp and level portion of the input signal I can integrate the curves to get the total power dissipated in the switching event. My original analysis carried this forward to derive a formula that described the maximum capacitance for various resistances and power limits.
While a relatively simple matter, my skills have unfortunately eroded and for some reason there is no readily available discussion of this topic. I would appreciate any assistance in resolving this problem.