Question about long rise and fall times for the Set/Reset/Data input lines to the CD4013 dual D flip flop.
The data sheet doesn't list maximum times for changes on the set/reset/ data lines for 4013. I understand the data may not be valid for voltages near the center of Vss , my concern is damaging the device with slow voltage changes near the mid Vss point.
Thanks,
-Bill
When you bias a CMOS inverter for linear operation, the input is biased at half rail, both P and N channel transistors are partially on and conducting current, but it does no damage.
At low voltages, it'll cost some power but won't hurt. If you try to do this at Vss =3D 18V, though, the possibility of exceeding the package power dissipation limit exists.
Safest practice is to use a Schmitt trigger (CD40106, or 74HC14, or MC14584) to condition slow-slew-rate inputs.
Yes, probably right, but I want to avoid adding extra parts. The thing runs at 5 volts, so dissipation probably not a problem.
Thanks,
-Bill
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Yes, good point. I hadn't thought of that.
Thanks,
-Bill
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