Hi all,
I would like know from the experts if the following behavior is possible if the input signal rise is exeeded. Xilinx states in its datasheet it shall be no more than 250 ns.
If it is for exemaple 350 ns, but still - single pole - monotonic rise time, what is the internal logic seeing? Is it possible that the transistion from "0-1" is being seen as something like "0-1-0-1", or is only a matter of power consumption in the CMOS input stage, or even something else?
Best Regards Markus