# fet rise/fall times

• posted

Hi,

What determines a fet's ie. 650V n channel like this one:

?name=IPP60R099CPIN-ND

rise and fall times?

I usually look at total gate charge to find fet driver current requirements for switching losses, and Rds(on) for on-time power losses, but haven't figured out the relationship between rise/fall times and these or other parameters.

I think rise and fall times must be proportional to the total gate charge and the gate drive currents, but it seems that maybe some fets have a minimum rise/fall time independent of the gate drive currents maybe.

cheers, Jamie

• posted

?name=IPP60R099CPIN-ND

Sort of. If you drive them with an ideal zero source impedances, i.e. one that can supply infinite current/charge, the fet will still have a mimimum on/off time. 1st, there is internal resistance in the gate which will limit the actuall maximum current possible, and hence speed, i.e. an Rgate.(Cgs + gain.Cgd) network on the input. 2nd, the output current is limited to Vgate.gm, and this finite current has to charge the output capacitances of the device (Cgd, Cdb, Cds, Cload).

```--
Kevin Aylward
kaEXTRACT@kevinaylward.co.uk```
• posted

That said, many OF TODAY'S high-voltage power MOSFETs will switch many amps over nearly a kV in 10 to 15ns, with a high enough gate-drive current, which is pretty impressive. The gate-spreading resistance info you need to determine in advance how well a given type of mosfet will do is not available. Jamie, you'll have to measure this yourself. What are you working on?

• posted

I can give you a couple of examples from instruments I've made lately.

First, an ON Semi MTW6n100E, rated 1kV 6A 1.3-ohms, driven from a TC4429 mosfet driver with a 1-ohm gate resistor (estimated 5A Miller gate current), switches 1.1kV and 11A into a 100-ohm resistive load (50-ohm source termination + 50-ohm coax) with a 15ns turn-on risetime. Turn-off time wasn't measured (note, this can be a problem, if active methods aren't employed).

Second, a pair of Fairchild FQA10n80 mosfets, rated at 800V 10A, driven by an ir2113-2 driver IC with a flying high-side driver, with 3.3-ohm gate resistors (estimated gate current, 1.3A), switch 600V 6A into 100 ohms (see above) with 30ns risetime and 30ns falltime. The ir2113 driver IC provides about 30ns of delay after turning off one mosfet, before turning on the other. Even so, there probably was some rail-rail shoot-through current, which could have been reduced or eliminated by adding Schottky diodes across the 3.3 ohms to speed mosfet gate turnoff.

From these numbers we can see that actual power mosfet gate spreading resistances are smaller than the values you usually see in the manufacturer's spice models, etc. However, modeling a power mosfet as a single element, with one spreading resistance is a serious mistake, as I've written about here in the past.

• posted

?name=IPP60R099CPIN-ND

Usually the marketing depatment :-))

But there are resistive paths internally.

```--
Regards, Joerg

http://www.analogconsultants.com/```
• posted

Thanks, I guess the datasheet rise/fall times won't trick me into buying a part that shows 5nS rise/fall now :)

I never heard of anyone using a 1 ohm gate resistor before, heard of people having difficulty with ringing using low gate resistances though :) Any tips on how to get away with such low gate drive resistance?

I am making a SMPS, and using overkill gate drivers (TC4452

12Amps!!) I have paralleled fets on each leg of the bridges, not sure if I will try to get away with 1 gate resistor for all the fets per leg or if its better to use 1 resistor right at each fets gate. Thanks! :)

cheers, Jamie

• posted

What part is that, with such a claim?

IXYS has made some that can do it. I've measured 5-8ns with some MOSFETs under ideal circumstances.

I would say the secret is keeping the gate-drive path inductance very low. Another is to force a very fast transition, faster than half of the potential oscillation period.

One gate resistor per mosfet, that's the rule. Break it with a high-voltage mosfet and get 20-to-40MHz oscillation as the drains traverse their voltages.

• posted

It's not a secret. It's a bold-typeface paragraph in every single datasheet and app note and text book on switching MOSFETs.

That's good advive, and not quite so obvious.

robert

• posted

Hi,

This expensive one: IPP60R099CP

?name=IPP60R099CPIN-ND

Ok thanks!

cheers, Jamie

• posted

BTW, that's 5ns, not 5nS (= nano Siemens)

OK, very good, worth a try!

• posted

099CPIN-ND

Interesting things about that mosfet, at Infineon's website: 1) The IPP60R099CP cannot be found using their site search. OK, wait, I take that back, after writing this, now it works.

2) According to Infineon factory "Product / Process Change Notification" document N=B0 2007-123-A, dated last Nov 2007, the IPP60R099CP was chosen as the "test vehicle" for process qualification at the new Kulim, Malaysia fab, because it was the "biggest Chip in TO220/TO262".

Normally large-die mosfets have too much capacitance to make fast switches. However, according to the datasheet fig 13, this part has Crss =3D 2.5pF (drain-gate feedback capacitance above 70 volts), which is amazingly low for a big die, let alone a common smaller one.

• posted

I broke that rule many times. Should I now stand in the corner, stare at the wall and feel ashamed of myself?

Depends on what kind of load is hanging off the drain. Also, if you pass EMI cert with good margins and the FET isn't stressed past any abs max during these bursts, who really cares?

```--
Regards, Joerg

http://www.analogconsultants.com/```
• posted

A good reason to care is the mosfet's health. When this type of oscillation happens, high voltages can be developed V = dI/dt on the fet's source bond-wire inductance, and depending on the osc. frequency and Ciss, the gate-oxide can be damaged. Goodby FET. It's happened to me and to others. So it's wise to avoid the scene entirely, even if the EMI is OK.

Now, as to whether you can sleep at night, worrying about your paralleled MOSFETs? Who can say?

• posted

At 40MHz that would have to be a lot of inductance. But I can see your point.

None of them ever exhibited such oscillation bursts and I tend to test the dickens out of any powerful switcher. Some are in production well over a decade, no problems.

```--
Regards, Joerg

http://www.analogconsultants.com/```
• posted

Since the FETs keep getting faster. I suggest monitoring production.

• posted

Joerg, the oscillation occurs in one to four cycles of RF during the time the drain voltage is swinging hundreds of volts, as the FET is transitioning on or off. It's hard to scope, but if you're very careful in probe and ground-lead setup, you'll see it on the source or gate leads. A 10-50MHz wideband RF sniffer coil can be a useful tool to detect trouble.

Paralleled high-voltage mosfets without separate gate resistors and/or ferrite beads are almost certain to oscillate if the risetime or falltime is long enough and the current is over 100mA. Consider f = sqrt LC, and a case with L = 10nH and C = 1000pF, f = 50MHz. Switching slower than 15 to 25ns without good damping management can be the beginning of serious trouble.

• posted

That's how I usually check things out, with an EMCO near-field probe kit. Always been quite, so far. And there have been a few switchers where I used RF FETs because they happened to be cheaper.

Ok, I see, but 15-25nsec transitions are considered sluggish in modern SMPS. Often I use a pnp/npn follower pair to goose things a little.

```--
Regards, Joerg

http://www.analogconsultants.com/```
• posted

And I use fairly-powerful mosfet-driver ICs.

Yes, 25ns would be considered slow for a low- voltage SMPS, but most commercial offline high-voltage designs that I've examined have been intentionally kept slower than that. A 360V dc bus being switching in 25ns is doing 15kV/us, which is considered a fast territory. It seems reasonable that a HV design working at high enough currents to require paralleled mosfets would fall into the slower category.

Joerg, you wrote "I broke that rule many times," can you say if your paralleled mosfets with a shared gate resistor, hopefully without trouble, were one of either: low-voltage, low-current, or sub-25ns switching designs?

• posted

I will, too. Once they drop to less than 20 Cents :-)

Vin is usually between 5V and 30V, Vout anywhere between zero (SEPIC and forward converter) and 100V.

Plus lots and lots of pulser designs for ultrasound. There you have to generate pulses in the 100-200V range into a stiff load down to 50ohms. No such luxury as gate resistors here, every fraction of a nanosecond counts. This stuff typically remains in production for more than a decade. The boards might change because FPGA don't have such longevity but they keep the pulser designs a long time.

It's all over the place. From coin cell operated gear to pulse peaks in the kilowatt range. Small stuff can require paralleling because of efficiency and to be able to still use very cheap devices, the big stuff sometimes because a single device would otherwise croak.

Usually not.

```--
Regards, Joerg

http://www.analogconsultants.com/```

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