rise and fall time

Hello everyone,

using a CMOS counter like 4518, I know that a maximum rise and fall time of

Thanks! M.S.

That should work fine. Except that 14/(46+14) is 0.23, so the reset line could rise to Vcc*0.23 during clocking, probably safe but a bit high for comfort.

John

No clock would be applied. It is a cheap way I'm experimenting to send clock pulses or reset pulse on the same line: clock input directly connected to this line and reset input through a 1mS RC filter. Sending short pulses (14uS on/46uS off in my case) would not be enough to rise significative voltage on reset input after the RC filter but clock input would work as intended. On the other hand, sending a long pulse (say 5mS to be sure) would rise voltage enough at reset input to reset the counter.

M.S.

It depends- this would not be advisable if the clocks are applied at the same time.

Very clever! That will work- just be sure that some other logic is not doing something with your counter outputs- they may not all go to '0' at the same time- there will be no problem coming out of reset.

I may consider this if it proves to be unreliable. I'm just trying to do as much as possible with less chips, otherwise I go with microcontrollers.

Thanks! M.S.

Hello M. Smile,

For greater peace of mind I would look into adding a CD40106 Schmitt inverter before each input. For the reset that would be after the RC filter. It is cheap. Just keep in mind that now the assertion levels will be inverted.

I have done a lot of slope dependent and duration dependent switching with CD40106 chips. They are great.

Regards, Joerg

Hello M. Smile,

Unreliable can mean all sorts of things here. It might work, and then some day it doesn't work with the next batch of chips. Or it might work and then quit when the chip temperature reaches some extreme. Going beyond the transition times outlined in the family spec is like playing the lottery.

Regards, Joerg