Dear Sir
Thank you for your help. But what is the fact that, I am an Engineering Student(Computer Sci.) and this above mentioned question is asked in the university examination in the subject Electronic Devices and Circuits(EDC) and I searched a lot for the particular answer , so that I can write the answer in the examination. However, I failed to get the answer in examination point of view.
The complete question is as follows
"Suggest a graphical procedure to establish the Q-point for JFET as a amplifier with voltage divider bias( 6 Marks)"
If you know any e-book or any website, that explains this answer and some other websites for EDC then please tell me.
Thank you, Ajinkya