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FPGA or shift registers?

hi,

I have a device with 34 digital (5V or 0V) inputs. Only one of the 34 can be 5V at any one time. I'd like to know the number of input which is at 5V. I can think of two ways of doing this:

a) 5 eight-bit shift registers. Each input is connected to a shift register and the shift registers are read and outputted one bit at a time periodically (left shifting the bits one bit at a time). b) programming a FPGA. It'll have 34 inputs and report the number of input that was tripped as output.

The disadvantage of method (a) is that it has more parts and also I was told that during the reading of the shift registers there might be an error where one bit is skipped, which will result in getting the wrong number for the tripped input. The disadvantage of method (b) is that I have no idea how to program a FPGA.

Can anyone recommend either of these methods (or a simpler one if it exists)? Is it likely that the skipping error in reading the shift registers will occur?

thanks, Jon.

Reply to
jonyt
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snipped-for-privacy@eng.tau.ac.il skrev:

Analog multiplexors is simpler, but still more parts if you stay with the inexpensive 8ch ones, and it will use up more pins.

3for control, 1for in and 1 for enable per chip.
Reply to
Jan Nielsen

Hi, Jon. Use 5 HC595s if you just want to get it done -- it's straightforward, and they work well.

The whole business about spurious data coming from shift registers is mostly people who've either done really sloppy layout, or are actually seeing noise at the input of the shift registers.

Keep all the ICs close to the controlling uC (or whatever you're using), and keep the control lines short and direct. Use common sense to provide power supply bypass caps for the HC595s.

If noisy inputs are a problem, you may want to use buffered inputs with schmitt trigger inputs. A small R-C at the input will ensure that noise is filtered out. Note that layout becomes important if you're filtering high frequency noise -- use a ground plane.

If you want additional safety factor, try latching and reading the inputs twice to see that they agree.

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Good luck Chris

Reply to
Chris

You could do it with 6X 74HC148 ($0.55 at DigiKey), if you can make your inputs active low. The data sheet

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will show you how to cascade them.

Good Luck! Rich

Reply to
Rich Grise

I would consider using a small CPLD as an FPGA would be mass overkill for your application. A CPLD would have other advantages over discrete logic in that it allows easy modification to the logic structure and can be tested and verified before you even put it on the board.

You mentioned being unsure how to program one. They are really quite simple. The programming can be done either with simple schematic capture, much like creating a board schematic, or through a text language like VHDL.

If you are still unsure, you can download a free set of development tools from either Xilinx or Altera, and experiment with them to see if you are comfortable. You could implement your design and then verify it with the simulators.

The actual programming process is done through the tool and utilizes a JTAG port. What this means is that on the board you would need to add an extra connector (about 10 pins, usually in an inline or .100"x.100" header to connect the programmer. Your only real expense would be a couple of hundred dollars for a programmer. If you are only going to do this one design, then I would consider the discrete logic as it is more cost effective. If you think this is something you would use in the future, I would suggest that the CPLD may be a good way to go.

Reply to
Noway2

[...]

no, not if it's constructed correctly,

OTOH

if only one of the inputs will be high at a time, you could just use a bunch of diodes and a few resistors to make a simple encoder.

another thing to consider is using some "priority encoder" chips.

Bye. Jasen

Reply to
Jasen

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