Digital equivalent for unity gain follower ??

You're on the right track; correctly sized (and placed) buffers (ie two inverters in series) are what you need. You can also construct a tree of these to drive multiple spatially separated loads.

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Buffer. Often buffers, or even single inverters, are put into long nets on chips to speed them up. Since wires are R-C transmission lines, the delay goes as the square of the distance. Buffers (or inverters, if there is an even number of segments) can split the line into several segments increasing the delay linearly with length instead of exponentially.

What was the problem. Inverters are generally the best solution since any pulse shrinkage caused by asymmetrical rise times cancels.

An hints at your problems would be if immense value. ;-)

Well, in CMOS, one can parallel inverters - so one inverter as the "buffer" driving the other 5 in parallel = one hex inverter package. A second hex inverter could be wired in parallel with the other 5, giving the drive of 11..

Figure out why this is only "partially helpful", because that's essentially what you're after - a non-inverting buffer which typically has two inverters; whether "in series" is the right term here, I've never seen a need for such a designation - I'd have said "In sequence" or "one driving the other" or some such.

Any hints, suggestions would be of immense value.

Tell us what your ideas are as to why the two inverters didn't give you what you want.

Thanks Rich

Thanks to each of you for your responses. I am trying to design a high speed (clock >

10GHz) shift register and I f> Figure out why this is only "partially helpful", because that's

At 10GHz, your connections are all transmission lines, and you have to worry about cross-talk and reflections. A 10GHz sine wave has a period of 100psec, and a wavelength in air or vacuum of 3cm. In printed circuit boaed dielectrics, this drops to 2cm. Any connection longer than about 1 cm needs to be treated as a transmission line and terminated with a resistve load where the resistance of the termination is equal to the characteristic impedance of the transmission line.

Data books for ECL logic always included application notes about treating connections as transmission lines, and advice on how to terminate them. Old TTL and CMOS data books never did, but modern CMOS is fast enough that you should be able to find application notes that cover teh subject.

Howard Johnson and Martin Graham have written two books on the subject

-"High speed Digital Design: A Handbook of Black Magic" ISBN

0-13-395724 and "High Speed Signal Propagation: Advanced Black Magic" ISBN 0-13-084408. Both are badly organised and badly written, but I don't know of anything better that addresses the subject in any detail.

Driving a capacitative load - such as a CMOS gate - is effectively driving a short circuit, and any edge going into the gate is reflected with inversion. Adding a resistive load in parallel to the receiving gate can reduce the reflected spike, but it makes life difficult for the driver, which probably isn't designed to source or sink direct current all the time.

Source terminating the signal, with a resistor between the driving output and the transmission line, puts less of a load on the driver, but slows the edge at the receiving gate.

I hope this helps.

-- Bill Sloman, Nijmegen

What inverters did you use ??

Check the data sheets of any inverter/non-inverter chip first.

These will be an output current parameter and an input current parameter.

Use them just like analog gain:

output current

--------------- = gain input current

You did check the data sheet first ??

h

It's called capacitive feed-through and can't be avoided entirely. It can be reduced by making the minimum sized structure that is still capable of driving its own feedback paths plus the following stage. ...Jim Thompson

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Bill Sloman schrieb:

Hello,

there are also transmission line effects with a quarter of the wavelength. Connections longer than 0.5 cm need to be treminated too.

Bye

If I understand your question.. We use current mode type outputs to assist the low driving current of devices.

For example; Instead of a follower, you drive a NPN common emitter mode transistor into saturation. This brings the output in the inverted state but it also allows for you to use a low voltage control source to pull a much higher voltage source, along with current boosting of course..

You don't drive the base directly, you need to bias it via an R to not over drive it when the signal source goes into forward bias. etc..

Depending on what type of signal you want in the end, (+) or (-), you select between NPN or PNP, both are in common E mode..

etc..

Mayiebe itz de-laiz..