zapping gates

Am I? Have you met a component which fails in "one and only" way in all places of usage?

Must be something special, "new, improved, buy it today!", a gate with conductors on two sides of insulator which has NO capacitive effects at any frequency.

Been there, done it. So is life, what can be done?

Just so long as your test procedure duplicated the environment of the failure mode being chased, and included a sufficient sample base to duplicate the rate of failures in evidence.

RL

Yes. The gate oxide punches through, and then you can push as much current as the wirebonds can handle.

No, not unless a huge amount of energy is available, in which case you get shrapnel. Serious SOA testing *does* make shrapnel.

I put a Fluke ammeter in series, but it's not necessary... the gate shorts the supply, it current limits, and voltage drops to near zero.

I thought the numbers were interesting, and thought others might have data on other parts. I didn't expect to get ragged over methodology, especially from a bunch of people who sound like armchair engineers.

John

one

I admit I am sitting in my armchair. I don't see why asking for more data should be offensive.

Not offensive, just very, very silly. I mean, I told everybody exactly what I did, like turning the pot on the power supply and reading the meter, and then people ask me stuff like what kind of supply I used, and how many volts/ns were applied.

Nobody has, of course, presented *any* other data. That would require actual interest or actual activity. In the "led as photodector" thread, a few people actually got off their butts and produced some numbers.

John

message

data

If I were to try to produce some other numbers, I would try to imitate as closely as possible your test setup and method. Thus the questions.

Also, if I were to get different numbers, I would look for differences intest setup or method as the first step to resolving the differences.

Hello John,

"the fet"? It would have to be "the fets" and probably a few hundred times x different batch numbers. To the tune of $10 each or so. It'll only be an additional $50k, or maybe $100k, nothing compared to the guy who had his Lamborghini nailed to the wall (did you read that one?).

Anyway, thank for sharing. Wouldn't have thought a FET could stomach four times abs max. Wow.

Regards, Joerg

[snip]

Amen. Let them go frag their own FET's. ;-)

--Mac

For those who are interested in this topic, it may be of value to read this document:

In particular section III. "Experimental verification" under the observations 1. and 3. will be of interest. Basically they claim standard gate MOSFETs typically are destroyed around 70-80V, with logic level devices around 45V-50V. Additionally, if gate avalanche currents are limited to a very small level (IE:

"Fritz Schlunder" wrote in news:e48kmp$h0g$ snipped-for-privacy@emma.aioe.org:

Interesting - Thanks for posting this info.

How do you get the figures to show? I tried Acrobat 5.0 and Foxit, and neither showed any images. The pdf header says it is "PDF-1.3", which I believe means it is version 4.0 so any viewer should work fine.

What's the trick?

Regards,

Mike Monett

there will be a gaussian distribution hiding in there too.

back when my employer used to give Hitachi AIC $1,500,000 per year, we got ALL of the factory data. spec'd lifetime is -3 standard deviations; mean lifetime was 2x rated lifetime.

Cheers Terry

Spehro Pefhany wrote in news: snipped-for-privacy@4ax.com:

I didn't think so either, but ya gotta be careful making hard and fast statements with this bunch. Someone (usually with the initials S.P.) will often post a reply to the effect you need to click on a hidden icon in the upper right corner, which opens a new menu, and so forth.

So I tend to weasel-word my posts as much as possible:)

Regards,

Mike Monett

I don't think they're in there.

Best regards, Spehro Pefhany

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John Larkin wrote in news: snipped-for-privacy@4ax.com:

So can you give us more info on the failure and any idea what caused the problem? Maybe ESD during handling? I understand this can cause a latent defect that fails later in service.

Regards,

Mike Monett

I like your musical expertise. OK. How about "armchair" in "Fouga Magister" (no parashute, "We don't need it at 6 meters above water" - the test pilot declaration) with the Honeywell UV recorder on my knees, to do some "armchair" testing at

600km/h.

Stanislaw Slack user from Ulladulla.

"John Larkin" a écrit dans le message de news: snipped-for-privacy@4ax.com...

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data

Hey, they forgot to ask what was the total RMS noise and its PSD, if it changed with the applied voltage, what was the leads inductance, the coupling factor between the D-S and G-S loops and also how many neutrinos crossed the die during the experiment.

That's the way I'd define the experiment conditions, plus some others I sure forget. Not very serious testing engineers, aren't they?

--
Thanks,
Fred.


> Nobody has, of course, presented *any* other data. That would require
> actual interest or actual activity. In the "led as photodector"
> thread, a few people actually got off their butts and produced some
> numbers.
>
> John
>

Un bel giorno John Larkin digitò:

Since this thread has gone a little polemic, please don't misunderstand me when I ask you (with all the good intentions): what were you trying to prove? If datasheet says Vgsmax is 30 V, I think it's safe to stay under

30V, no matter how conservative are the absolute ratings. What good will make (in general and in your specific case) to know that a single model withstood 115 V?

--
asd

Interesting; thanks for the link. It's a pretty wordy paper, but the conclusion...

VI. Conclusions The use of a capacitive discharge into the gate to identify ESD sensitivity of a MOS-gated transistor does not seem to provide any additional information beyond what can be obtained more accurately from a curve tracer and simple calculations. It is recommended that, for MOS-gated power transistors, the ESD test circuits shown in Figure 2 be replaced by a simple dielectric strength test performed with a curve tracer, completed by simple calculations, as per Figure 3.

implies that rate effects aren't important.

There's no date on the paper, but they do refer to a "memoscope."

John

[snip]

Except that the actual failure mechanism is most likely metal migration through "pin holes" in the oxide. "Rate" will cause hot spots and thus affect the failure mechanism.

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
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