It can shift power dissipation. The old Tek tube scopes did that a lot in the power supplies.
Sometimes a series resistor, in the input of a transistor or a regulator, will reduce worst-case dissipation, and it's an opportunity to noise filter too.
-- John Larkin Highland Technology, Inc The best designs are necessarily accidental.
response in the feedback loop. I saw a board design that used an op amp and an n-FET as a linear regulator. The power source to the pass FET was a swi tcher to prevent a lot of dissipation and the op amp was powered from the 1
2V input so there was plenty of drive to the gate. The reference voltage wa s the same as the output voltage, so with the FET in a common source config uration there was no gain other than the op amp which has a 1 MHz gain-BW p roduct..ntrol loop to have minimal impact on noise from the switcher. However, even though the FET configuration has no gain from gate to source, it should ha ve gain to minimize the transmission of noise from the drain to the source. Raising the drain voltage will increase the current raising the source vol tage. Of course that reduces the gate-source voltage which acts to prevent the source rise... however, that is without considering the FET capacitance s.
to allow the drain noise to transfer through to the source. Is there a rea sonable way to mitigate this effect? Someone suggested adding capacitance t o the gate to swamp out the effect of the gate-drain and gate-source capaci tances. If that can be done without impacting the response of the control l oop, it seems like it might work. Or is this doomed to fail because it *wil l* impact the control loop at a level before does what is intended?
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Huh OK, I'll have to try it. Thanks.
Right, I've done that some. First to mind is a class A current source for driving ~1 ohm coils. 1Amp max and only +15V supply.
10 ohm resistor, burns power but it did make the coils snappier (L/R time)George H.
No, the resistor is in series with the collector, and the capacitor goes from there to ground. At very high isolation, junk gets in via capacitance and the Early effect otherwise. (BJTs are good that way, but not 150 dB worth of good.)
It's sometimes useful to put a largish resistor from base to emitter to make sure there's enough CB bias for good performance--since it's got a BE drop across it, it's a reasonably-constant current source. That's needed especially when using a 2-stage cap multiplier, because without it the V_BE of the first stage puts the second stage into saturation. (Assuming that you use a single RC ladder for both bases, which you should.)
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net http://hobbs-eo.com
esponse in the feedback loop. I saw a board design that used an op amp and an n-FET as a linear regulator. The power source to the pass FET was a swit cher to prevent a lot of dissipation and the op amp was powered from the 12 V input so there was plenty of drive to the gate. The reference voltage was the same as the output voltage, so with the FET in a common source configu ration there was no gain other than the op amp which has a 1 MHz gain-BW pr oduct..
trol loop to have minimal impact on noise from the switcher. However, even though the FET configuration has no gain from gate to source, it should hav e gain to minimize the transmission of noise from the drain to the source. Raising the drain voltage will increase the current raising the source volt age. Of course that reduces the gate-source voltage which acts to prevent t he source rise... however, that is without considering the FET capacitances .
to allow the drain noise to transfer through to the source. Is there a reas onable way to mitigate this effect? Someone suggested adding capacitance to the gate to swamp out the effect of the gate-drain and gate-source capacit ances. If that can be done without impacting the response of the control lo op, it seems like it might work. Or is this doomed to fail because it *will
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OK so this is after the node that feeds the base RC, and the Vbe drop of which you spoke is because I can run the collector a little closer to the emitter than the base is ? (Vce base resistance to be as big as possible. (I'm now wondering about this. the bad thing about big R_base is it gives the low noise supply a larger source resistance.) Big R_base gives me a long time constant for a given capacitance
2.) I then take the max current, (let's say 100mA, cause that is one I did. ) 3.) and a conservative guess at current gain, say 100 for the 2n4401 4.) and at max current I want less than/about a volt of drop across R_base So for this example that's 1V/1mA = 1k ohm. 5.) I wanted it to have a LF time constant of ~100ms so C_base = 100uF. Now that I'm almost done, I think it was the 100ms TC that drove the desire for large R. Two RC stages of 100ms does a nice job of knocking down the 60 Hz. crud. 6.) you build the thing, see how it works, tweak if needed.
d.) Huh.. do you get phase shift issues inside a two stage thing? The last thing you want is to make anything close to an oscillator.
George H.
The two are simply in cascade. There's no feedback to speak of. For a two-stage cap multiplier, you just go
Q1 Q2
0-*-R1R1---*----* *--------* *----*--0 | | \ A \ A | | giant CCC ------ ------ | | alpo CCC | | | | | | | | | GND | | bias | | | | | *-R2R2--*---R3R3-*--R4R4-*-R5R5-*--R6R6-* | | | | | CCC CCC CCC CCC CCCC giant CCC CCC CCC CCC CCCC alpo | | | | | GND GND GND GND GND(Extra points for using quad pack resistors intelligently.)
You pick the bias resistor R6 such that R4+R5 drop enough to keep Q2 from saturating.
Good transistors include the 2SD2704K for currents below about 20 mA, and its big, low voltage brother 2SD2114 up to 500 mA or so. They're both low-sat superbeta devices, although slow as molasses, which puts more of a demand on the alpos' high frequency behaviour.
You also need some input protection, because folks will inevitably short the input to ground or attach a car battery to it.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net http://hobbs-eo.com
In practice, its more subtle than this, such that the raw gm of the output devices is not a key factor in the regulation design of a regulator. indeed, a typical problem is that the gm of the output device, even for mosfets, is too high.
The stability and dc regulation of the regulator is a function of ALL of the gain stages in the loop. It doesn't really matter where this gain is distributed as far as the basic regulation of the system is concerned. Internal DC gains of 80 dB-100 dB isn't usually a problem to achieve. However, large DC gains, even with compensation, translate to tricky stabilisation issues.
The "low" output resistance of a bipolar in emitter follower mode is also an illusion. It only achieves this low resistance because it has an internal feedback loop of output current to input emitter voltage. The raw output resistance of a bipolar is high, because it is fundamentally a voltage controlled current source. To analyse the loop, all loops need to be broken at once. This is analysed here:
-- Kevin Aylward
:
response in the feedback loop. I saw a board design that used an op amp an d an n-FET as a linear regulator. The power source to the pass FET was a sw itcher to prevent a lot of dissipation and the op amp was powered from the
12V input so there was plenty of drive to the gate. The reference voltage w as the same as the output voltage, so with the FET in a common source confi guration there was no gain other than the op amp which has a 1 MHz gain-BW product..ontrol loop to have minimal impact on noise from the switcher. However, eve n though the FET configuration has no gain from gate to source, it should h ave gain to minimize the transmission of noise from the drain to the source . Raising the drain voltage will increase the current raising the source vo ltage. Of course that reduces the gate-source voltage which acts to prevent the source rise... however, that is without considering the FET capacitanc es..
p to allow the drain noise to transfer through to the source. Is there a re asonable way to mitigate this effect? Someone suggested adding capacitance to the gate to swamp out the effect of the gate-drain and gate-source capac itances. If that can be done without impacting the response of the control loop, it seems like it might work. Or is this doomed to fail because it *wi ll* impact the control loop at a level before does what is intended?
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Thanks Phil, Can I ask a favor? Could you send the above ascii art to my e mail? I have found it hard to de-scramble the above. Google takes out the spaces ... I try and put them in to make the picture make sense... but... Has anyone found a way to recover the ascii art in google groups?
George H
If you don't need a lot of current, why not use one quad r-pack and 5 caps? Current limiting is free.
-- John Larkin Highland Technology, Inc The best designs are necessarily accidental.
They totally screwed up all the Python code posted over the years, too. In Python spaces are part of the semantics. They could just have run-length encoded the spaces, but noooooo.
I posted the ASCII at . There's also an LTspice file there from five or so years ago,
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net http://hobbs-eo.com
email?
s...
This was not a problem under the old interface. I was able to continue usi ng the old interface for some time after they switched because I leave a wi ndow open and simply access each group when interested. I found in another window that a reload retrieved the new interface, but was able to use the historical window for over a week before it ran into a GG bug that required a reload. If someone could figure out what changed in the web page code, perhaps another source of the interface web code could still access the GG data? Or we could use another client altogether and forget about GG.
The guy who makes and sells the Beagle Boards used GG for his support chann el. I don't know if he still does or if Google screwed him over. There is a GG for EV charging with various categories and lots of info. I think so me of the more recent changes make that group much harder to use. So it's not all just issues with newsgroups.
One of the nice features of GG is the fact that it is based on a browser, s o when a link appears it is easy to open or a phrase is easy to research or a word to lookup. My spelling is horrible and the common spell checker on my machine (don't know if there's a common one for all the apps or if they each have their own, I've never figured that out) is pretty stupid not kno wing many, many common words. Before I shove a new word into the dictionar y I check the spelling with a web search. Easy peasy while in the browser.
-- Rick C. -- Get 1,000 miles of free Supercharging -- Tesla referral code - https://ts.la/richard11209
In other words, use a pi filter to the collector of the capacitance multiplier... because this is about backing up an already-filtered DC supply, isn't it?
Very good.
This shows the ripple at the collector of Q2, and the resulting ripple at the output in uV:
-- The best designs occur in the theta state. - sw
Usually because I need to power some glorified CPH3910 JFET stage that takes 20-40 mA altogether. BF862s work great at about 10-12 mA, but the
3910's I_DSS is much higher. Occasionally I power part of the circuit off the first cap multiplier stage and part off the second, but I've only done that once or twice. You get a nice bit of isolation between the two parts, but you have to waste some headroom making sure that the load variations on the first stage don't push the second into saturation. Even a little bit of beta modulation makes a big difference there.The overall issue is that single-ended discrete stages have little or no PSR, so the cap multiplier has to carry the freight.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net http://hobbs-eo.com
Generally it's to turn a switcher rail with ~100 mV ripple and lots of other junk into something suitable for ultrasensitive measurements (~30 nV ripple, ~1 nV noise in 1 Hz). See the stuff I posted upthread.
Back in the palmy days, we ultrasensitive measurements folk could just say "You have to use a linear supply" and make that stick. Not any more.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net http://hobbs-eo.com
An emitter follower has voltage gain slightly less than one, so 'gm' isn't really a relevant specification there; the overall feedback loop was stable because of the 'slow op amp' parts, which operate within the 'useful range of frequency response' while the cap multiplier operates above that range.
True enough. I've seen some applications where it takes mercury-based batteries to get low noise, and temperature control, and.... Gain isn't free if you value low noise.
An low power, a noise cancellation circuit might make more sense.
It shouldn't require headroom, being capacitively coupled, just impedance isolation from the noise source, over the frequency band of interest.
RL
It is relevant. I explained why. A feedback system containing an emitter follower doesn't work how most assume it does.
....as I explained, the "unity gain" concept of an emitter follower is erroneous in feedback analysis. It doesn't directly account for the stability of a feedback amplifier.
as I noted, to understand the technical point, you really should read this:
It needs to be understood, as I stated, that an emitter follower only looks like it has low output resistance is because it is a negative feedback system. A bipolar transistor is inherently a current source.
The essentials of a regulator, with an emitter follower output is that one has an amplifier 1, with gain. It feeds another amplifier 2 that, essentially,looks like an op amp with 100% feedback. There is an overall feedback loop from amplifier 2 to amplifier 1. Its a dual loop system.
The second amplifier, is the output emitter follower. To understand the stability of the system, one must break BOTH loops at once.
The loop gain will then seen to be LG=A1.gm.Zload
The "raw" gm is not a key factor in the *regulation* specification, because its the product of A1.gm.ZL that matters. If the gm is not that which is required, then the gain A1 can be changed. However, the gm itself is indeed a key component that needs to be addressed to stabilise the system.
If the system actually used a collector output, the basic transfer equation would, essentially, still be the same.
The advantage in the case of using an emitter follower in practice, is that additional AC feedback can be placed from the bipolar base back to the main negative input, thus taking the transistor out of the loop for high frequencies. This cannot be done for the collector output topology. The disadvantage of the follower topology, is that that one cannot achieve a low dropout voltage.
-- Kevin Aylward
Thanks Phil, I was picturing a Darlington or Sziklia, so had no hope of reconstructing the right pic. (the quad resistor pac should be all the base resistors.. I don't think the order makes much difference. It's a filter... keep input away from output. I'd do a string.) George H.
The AC magnetic stuff* in linear supplies was a pain. There is something to be said for a brick on the rope switcher... where you can put the supply over there... and just have to worry about filtering the electrical path.
George H.
my email?
paces....
I don't know about googlegroups but I'd just copy the text, paste it in an editor and change the font to 'fixed width'. Veritable width fonts will screw ascii art to bits
___o00o__( )__o00o___
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