Slowing FET edges

Just a gate resistor is usually all you need to slow down the edges. That's safer for the gate, too. Cd-g is free!

Not to change the subject (not me!) but phempts and GaN fets have almost zero Miller capacitance. That enables circuits that, by the usual standards, look totally stupid.

--

John Larkin      Highland Technology, Inc 

The best designs are necessarily accidental.

snipped-for-privacy@highlandsniptechnology.com wrote in news: snipped-for-privacy@4ax.com:

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edges.

Add a toroidal choke before the 100 Ohm resistor or the 10 Ohm. Small, and about 7 turns of say #20. Back off one turn at a time till you get it 'tuned'. Also, if it drives a transformer at the output, you can place a thin gap in the core halves to spread the switching point 'edges'.

Oh wait... that is for dual FET driven applications.

The choke will kill any hard start problems though.

What transistor?

Modern MOSFETs have such aggressive C(Vdss) curves that rise/fall times can peak at many times d(Vgs)/dt. Miller effect mostly occurs at low Vds. Gate resistance helps reduce dI/dt (because dVgs/dt ~ dIds/dt) but Vds depends on load impedance, and with low node capacitance at higher Vds, you get that.

Though 2 and 3ns is rather unbelievable. Also it won't be 25S at 1A, note the test condition; but still pretty sizable.

Yes, R+C feedback is a good way, you get something like a transresistance integrator so it's easily controlled by drive current, and is relatively independent of load impedance. (The R will usually be inconsequential, but omission all but guarantees oscillation. :) )

Also if you put a zener on there (to limit Vgs, in applications where that's desirable), it's also likely to cause oscillation, so add a gate resistor or ferrite bead. Possibly a FB would do for the Miller cap too.

Tim

-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Design Website:

I would've needed a stupid-big resistor, which I didn't trust to not sing.

I like the Miller arrangement. It swamps the device characteristics, so it's super-repeatable.

That's their appeal! This was a plain ol' MOSFET, fat for low Rds(on). The low Cdg for such a fat FET surprised me--they are still improving MOSFETs after all this time, which is amazing.

Cheers, James

Infineon BSC120N03LS. 30V, 12 milliohm, Cdg = 18pF.

Cheers, James

The bigger the resistor, the less it wants to oscillate. Gate current is typically electrons per second. A couple of kohms will slow down the edges, and save several cents.

Yeah, the zero-voltage-switch solutions with AC power really solve heater control nicely, if you can deal with PWM at a few seconds cycle time. Easy to just buy a SSR that will do it all for you. Or build one.

I'd have needed about 5k, but with a complex load in the drain and significant feedback capacitance, I didn't trust it to not become an r.f. transmitter in the transition zone.

Cheers, James

The heater supply is +12VDC; the spec requires three selectable voltage-independent regulated power levels, two indications and shorted-heater protection; the BOM budget was $0.50; and the finished board size is 0.75 x 1.25".

Cheers,

James Arthur

I guess it's hard to breadboard those LGA fets. I usually just try it.

I have never seen a switchmode transient problem that a bigger gate resistor didn't fix!

--

John Larkin      Highland Technology, Inc 

The best designs are necessarily accidental.

That's encouraging. I've never needed such a large gate resistor, and after seeing the load behaving so inductively-differently-than-advertised, I was leery of making the FET scream.

I probably shouldn't have been so paranoid. The source is grounded, so the usual Colpitts-style oscillatory feedback (e.g. in emitter followers) is blocked, and a big R-gate prevents common-gate oscillator modes.

Thanks John.

Cheers, James

Of course, the switching losses will go up with a big gate resistor.

Paranoia is best in this business. So many things can go wrong.

Once the power dissipation during switching starts getting appreciable, a bigger gate resistor is contra-indicated.

Slower switching times mean bigger switching losses, and at some point you run the risk of cooking the switch.

--
Bill Sloman, Sydney

Hmm, Coss ~ 400pF and 1A gives a rising dV/dt of only 2500 V/us (e.g., 50V in 20ns). Are you sure of 2ns?

Falling can be much sharper (only slowing noticeably by a few volts, where Crss rises into the 100pF range). Let's see, 12V/1us on a 1nF gate implies it'll blow through the Miller step (such as is is, on this one!) in maybe

100ns, which doesn't sound very fast. Even if a tenth of that is most of the drain voltage swing (plausible given the Crss spread?) that should still only be 10ns.

Tim

--
Seven Transistor Labs, LLC 
Electrical Engineering Consultation and Design 
Website: https://www.seventransistorlabs.com/ 

 wrote in message  
news:a56951f3-84ec-48e8-8e68-45c141d0a379n@googlegroups.com... 
> On Wednesday, January 27, 2021 at 6:02:19 PM UTC-5, Tim Williams wrote: 
>> What transistor? 
> 
> Infineon BSC120N03LS.  30V, 12 milliohm, Cdg = 18pF. 
> 
> Cheers, 
> James