What is tPA and tJitter in ADC?

Question

I'm trying figure out the sample and hold time of an ADC. In other words, not the sample rate, but how fast the sample and hold works. I'm comparing two chips.

Chip #1

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tAP (Sample-and-hold acquisition delay time) is 0 ns. tJitter (Sample-and-hold acquisition delay time jitter) is 0.2 psRMS.

Chip #2

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Advertises a 250MHz Internal Sample-and-hold tAP (Sample-and-hold acquisition delay time) is 3 ns. tJitter (Sample-and-hold acquisition delay time jitter) is 5 psRMS.

Could someone please explain what this means? I didn't see any sample and hold frequency for Chip #1. I can understand why ADC need a sample and hold because the signal is most likely changing. So the ADC wants to work on a non-changing voltage. Chip #2 explanation of the sample and hold seems easy to understand-- 250MHz. If we associated a frequency to chip #1 then what would that be?

Thanks, Paul

Tim Wescott · Accepted Answer

?navId=H0,C1,C1155,C1001,P1644,D2894tAP is shown in the "Timing Diagram" on page 11 of your first data sheet.  It has nothing to do with the highest sample _rate_ of the thing, just the apparent amount of delay from the clock.  It doesn't necessarily have anything to do with the sampling _rate_ that you can get from the chip as a whole -- since that rate is determined by the converter architecture the performance of the actual sampler is moot.tJitter is just what it says -- the amount of timing jitter that you can expect between your clock input to the chip and the chip's response _assuming that you drive the chip as specified_.  Any timing jitter here will multiply by the slope of the incoming signal and appear as noise in the reading.-- Tim WescottWescott Design Services

Andrew Holme · Answer

?navId=H0,C1,C1155,C1001,P1644,D2894Datasheet #1 quotes the "full power bandwidth" of the input circuit as 640MHz.

What is tPA and tJitter in ADC?

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