What are the optons.... ?

Hmm.. not exactly "magic"... i did something not unlike this back in the 80's with pld devices and eproms..

why not try a modern cpld or low end dsp ?

Texas Instruments MSP430?

What I really need is a cross between a PDP-8 and a PIC, only simpler and cheaper.

What's the minimum time between the required output edges?

Best regards, Spehro Pefhany

That depends on the number of harmonics being zeroed and the amplitude being sought.

Precise multiples of 100 nanoseconds delay from 3 to 4095 or more would be a good starting point. 20 or 50 nanosecond resolution would be even better. With (crucially) minimum overhead.

The situation is a little strange, because you are using the uP CLOCK as a DATA input, setting the output frequency reference.

A ONE CYCLE error can totally trash your harmonic results. Because of the ultra-exotic math involved.

Please see

Limitations of current code with PIC are amplitudes less than 4 not yet realizable and high rejected harmonics create code pinch points.

Plus the "smoke and mirrors" tricks to get precision 12 bit results from

Otherwise, all the chip does most of the time is output a pattern, delay, output a new pattern, delay, .... wash, rinse .... forever and ever.

Also see

It's magic because Don presents it in a way that doesn't make it immediately obvious to the standard Signals & Systems 101 matricular how it works -- plus he's come up with a decent optimization routine for the synthesis part and sells PICs that have already done all the heavy lifting for you. All-in-all, a very nice technology, and -- like Don's always done -- the price is right. I met a guy a couple years ago who was making a several kilowatt inverter using "magic sinewaves," and the videos he demonstrated of how well it worked were quite impressive.

I second your suggestion of a CPLD, although when one starts talking about "zeroing the 100th harmonic" you really have to start looking at stuff like timebase stability, I imagine.

Haven't looked at timebase stability too close, but I feel it probably would not be too big a deal.

For 28 harmonic rejection, clock stability has to be somewhat better than one part in 44,000. For 100 harmonics, perhaps four times this.

Probably becomes crucial if you want to zero the first thousand harmonics. Even then, reducing harmonic #993 by a few decibels shoudn't be that difficult a filtering problem.

This sounds like just about the ideal reason to get into FPGAs. Xilinx, for example. I don't think the hardware on most low-end controllers is going to help much. You can get 1 instruction cycle resolution, but to service an interrupt and reload data for the next transition might take a few microseconds, so it wouldn't be able to handle your runt pulses of less than that width.

Now, the MSP430 has a new feature on some of the higher end units that they call DMA. It's an engine which is triggered and steals cycles from the processor to transfer data from one place to another. You might be able to create a table containing the pattern and send it out, but the resolution would be limited by the available memory, which maxes out around 64K. There's also some jitter in the latency, IIRC, which may not suit you well.

If you want to stay with the hard-coded delays varying clock frequency, a 25u PIC24H will give you up to 40 MIPs (25ns) resolution, without a lot of new tools or learning curve.

Another idea would be to get rid of the micro entirely and just use a fat EPROM or flash memory and a counter to feed the address bits, plus a latch to hold the output data. The n bits wide could give different amplitudes through a mux. Do all the processing up front before it gets burned into the memory. An 80ns OTP EPROM 256K x 8 costs USD $1.28 at Digikey in 1K, and that should give sufficient resolution. Flash is a bit more.

Best regards, Spehro Pefhany