VCO buffer

I'm designing a 40-70 MHz synthesizer using the Mini-Circuits POS-75 VCO. The VCO output varies from 9 dBm at 40 MHz down to 7 dBm at 70 MHz. My circuit needs to provide isolation, tolerate open and short-circuit loads, and deliver 15 dBm into 50 ohms across the tuning range. What do folks think of the solution below? In particular, what about C2? This "hack" seems to compensate for the input level variation; but I don't know if it will work for real. This is for very low volume production and C2 could be set-on-test.

Version 4 SHEET 1 1308 680 WIRE -304 48 -400 48 WIRE -240 48 -304 48 WIRE -112 48 -176 48 WIRE 48 48 -32 48 WIRE 160 48 48 48 WIRE 272 48 160 48 WIRE 480 48 368 48 WIRE 624 48 480 48 WIRE 976 48 864 48 WIRE 1072 48 976 48 WIRE -400 80 -400 48 WIRE 480 80 480 48 WIRE 624 80 624 48 WIRE 864 80 864 48 WIRE 48 144 48 48 WIRE 160 144 160 48 WIRE 1072 160 1072 48 WIRE 480 192 480 160 WIRE 624 192 624 160 WIRE 624 192 480 192 WIRE -400 224 -400 160 WIRE 320 224 320 112 WIRE 624 224 624 192 WIRE -400 352 -400 304 WIRE 48 352 48 208 WIRE 160 352 160 224 WIRE 320 352 320 304 WIRE 624 352 624 304 WIRE 864 352 864 160 WIRE 1072 352 1072 240 FLAG 320 352 0 FLAG -400 352 0 FLAG 624 352 0 FLAG 160 352 0 FLAG 1072 352 0 FLAG -304 48 IN FLAG 976 48 OUT FLAG 864 352 0 FLAG 48 352 0 SYMBOL voltage 624 208 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V2 SYMATTR Value 12 SYMBOL voltage 320 208 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V3 SYMATTR Value 3.3 SYMBOL res 144 128 R0 SYMATTR InstName R3 SYMATTR Value 100 SYMBOL cap -176 32 R90 WINDOW 0 0 32 VBottom 0 WINDOW 3 32 32 VTop 0 SYMATTR InstName C1 SYMATTR Value 1n SYMBOL res -16 32 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R4 SYMATTR Value 50 SYMBOL res 1056 144 R0 SYMATTR InstName R5 SYMATTR Value 50 SYMBOL res -384 176 R180 WINDOW 0 36 76 Left 0 WINDOW 3 36 40 Left 0 SYMATTR InstName R7 SYMATTR Value 50 SYMBOL ind2 608 64 R0 SYMATTR InstName L1 SYMATTR Value 16µ SYMATTR Type ind SYMBOL ind2 848 64 R0 SYMATTR InstName L2 SYMATTR Value 1µ SYMATTR Type ind SYMBOL npn 368 112 M270 SYMATTR InstName Q1 SYMATTR Value 2N3904 SYMBOL res 464 64 R0 SYMATTR InstName R1 SYMATTR Value 800 SYMBOL cap 32 144 R0 SYMATTR InstName C2 SYMATTR Value 150p SYMBOL voltage -400 208 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value SINE(0 1.4 70e6) TEXT -248 192 Left 0 !.tran 0 150n 50n TEXT 696 48 Left 0 !K L1 L2 1 TEXT 648 8 Left 0 ;Mini-Circuits T16-1 TEXT -344 344 Left 0 ;or SINE(0 1.8 40e6)

Reply to
Andrew Holme
Loading thread data ...

What's the matter with posting a schematic to a.b.s.e?

Jim

-- "It is the mark of an educated mind to be able to entertain a thought without accepting it." --Aristotle

Reply to
RST Engineering (jw)

Done.

Reply to
Andrew Holme

All that for a clock for an FPGA? Which FPGA has a sine wave clock input rated in dBm???

Reply to
a7yvm109gf5d1

No and none.

I'm using an LVDS-output comparator for that.

The sine wave output goes elsewhere.

Reply to
Andrew Holme

A LOT of people have lost the a.b.* tree due to a few over aggressive state AGs and wimp ISPs. Damn, have you no memory?

Reply to
JosephKK

More like AGs giving ISPs an excuse to stop providing a service which has significant overhead[1] yet which most of their customers never use.

[1] 4.6TB/day, which equates to roughly 500Mbit/sec continuous bandwidth usage, plus all of the servers and RAID arrays needed to process and store all that data.
Reply to
Nobody

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.