Variable amplitude clock?

Mar 17, 2008 27 Replies

I have a project where I need to design a clock circuit that has variable amplitude (from ~1.2V - 3.3V). The input clock to this variable gain stage would be 3.3V, but I have to be able to scale it down to 1.2V if necessary. Digital control of the gain would be nice, but not necessary. The clock would need to be ~50Mhz max.



Some options I was thinking of...



- Opamps/variable gain amplifiers come to mind, however, I don't think they would work well with square waves - would they?



- I could maybe use discrete FETs and use an independent voltage supply to the FETs that I can program digitally



- Using a high-speed DAC would be good, but I'm not sure if jitter would be a problem here. WIth a DAC, I could control the high and low levels precisely, which seems to be the best solution... rise and fall time maybe an issue to.



Does anyone know how this is typically done with function generators etc?


At 50MHz and fast transitions? No. Or at least not at reasonable cost. The Rolls-Royce Deluxe version would be a fast VGA from Analog Devices but it would likely set you back around $5 or more.

Servoed FETs is what I did a lot. Then one fine day the SD5400 became expensive and nearly unobtanium :-(

Alternatively you can use an open drain logic chip and switch resistors in an R2R fashion.

Jitter depends on the quality of your layout, mostly. Must be RF style. Another trick with a slowish and cheap DAC is to take a current source version where you can use the resistor ladder as a "digitally controlled resistor".

Don't know, but there is yet another option: Digital potmeters. They have become quite cheap and you can clock in which tap you want. The number of taps is limited though, often there are only 64.

Regards, Joerg http://www.analogconsultants.com/

Thanks for your reply, very helpful!

Some responses...

  1. Firstly, cost isn't a factor (isn't that nice!). So if a fast VGA from ADI would work, then that's worth considering... the only thing is I don't think I would be able to add a common-mode with this setup, unless I passed it through a level-shift stage, right? This is still a good option though if it would work.
  2. I like your idea of open-drain logic...the only thing I would be afraid of here is if I'm interfacing to a non-high impedance load, or even a current drive clock receiver. With a VGA or DAC, this shouldn't be an issue.
  3. The other problem I thought of with a DAC is that it doesn't really let me control the frequency all that much. If I use a 100Mhz DAC, I can get a 50MHz clock, but I couldn't get a 40, which would be key. Unless there are advanced techniques that could be used that I'm not aware of.

Currently, the clock generati> jdhar wrote:

Who the hell knows how it's "typically done with function generators etc"- you could try something like this, but it's getting close hitting

50MHz at the low voltages, will depend on your loading. Have you omitted a minor detail like it's supposed to be a 50R driver, if so then back it up with a standard series terminated video amp: View in a fixed-width font such as Courier.

. . . . . . Vamp>--------+-||--. . | | . | --- . | com . |\\ . CLK >------| >------>VAR_AMP_CLK . 3.3V |/ . LOGIC | 74AUP1G34 . | . --- MOS gate with overvoltage . /// tolerant inputs . .

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. . . . . .

Most welcome. Just a suggestion: It is better to respond below quotes, makes it easier for other to follow and contribute some more ideas.

Many AD chips are differential, others contain two VGAs on one chip. But you have to find one that can swing a few volts at the required speed. So the slew rate would be one parameter to take a look at.

Many logic chips feature an RDSon of 30ohms or less.

Ok, I didn't know you want to control the frequency with the DAC. That tends to become expensive. Well, at least for my usual BOM budgets.

A VGA is probably the easiest solution if you can find one that is fast enough at the maximum desired output level. Then all you need in addition is a slow serial DAC to set the gain from your controller.

Regards, Joerg http://www.analogconsultants.com/

If you do that add a resistor in series with the input in order not to exceed the substrate diode abs max ratings. And don't let Jim Thompson see that ;-)

Regards, Joerg http://www.analogconsultants.com/

Right, if matching, low skew, and jitter are concerns then you will need to stick with clock driver product lines. Check with

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and
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for a start...

That's NOT how overvoltage tolerant logic works!

If it's a level translator, ok. But the datasheet only says 3.6V I/O tolerant, not much more info other than a substrate diode 50mA abs max:

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I wish they would give as much info as they used to in the good old days, with a circuit diagram ans such.

Regards, Joerg http://www.analogconsultants.com/

There are lots of TinyLogic type gates that will work from 1.8 to 5 volts power, and tolerate up to 7 volt inputs. I'd suggest using a variable dc power supply (LM317 plus trimpot, or 317 programmed by a DAC) to run one of these gadgets.

You might want to use a schmitt gate and/or divide down the output a bit, depending on your details.

Oh, you could also just start with a 3.3 volt swing and scale it down with a trimpot, 100 ohms maybe...

3.3v or so | |\\| | \\ in-------| ----------+ | / | |/ / pot \\

That's what Fred was saying. How do they do that?

Regards, Joerg http://www.analogconsultants.com/

See document page 4. in

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or somthing like this with two supplies:

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-Lasse

Thanks John. I think that wouldn't work in the case where the clock receiver pulls any current since it's just a passive divider, correct? Taht would only work in the High-Z case.

What does the variable clock have to drive?

Thanks. They don't have the AUP family by they mention the AUC famil;y to be overvoltage tolerant up to 3.3V.

Regards, Joerg http://www.analogconsultants.com/

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