USB digital scope

Hi Helmut, I try to summarize the DSO features (let me know if you have particular questions about some points)

Digital storage oscilloscope features:

- Data connection via USB 1.1/2.0 (FTDI - FT245BM)

- All DSO function are under PIC (16F8777) and FPGA (ALTERA Acex -

30Kgates)

- DSO A/D converter: 2 channels/12 bit: 20MSPS Real Time - 1GSPS equivalent time

- TTL external trigger

- Timebase from 200ns/div to 2sec/div, over 100ms/div roll mode

- Vertical scale from da 50mV/div to 50V/div

- Channel coupling DC,AC,GND

- Data acquisition: sample, low pass filtering, peak to peak

- Trigger from CH1,CH2 or EXT

- Tigger mode NORMAL,AUTO,SINGLE

- FPGA configuration via USB (possibility to change the DSO firmware in any moment)

- Powered via USB

- Small dimensions (145mm X 85mm X 30mm)

How can I send to the group the schematics, the images or some other attachements?

Hi,

Davide

hi,

Davide

Helmut, I forgot two more things:

The PCB is intended to mount also two 12 bit 50MSPS A/D converter (I do not yet tested this A/D converter but I hope this works fine...) in place of the two 12 bit 20MSPS; The PCB has an "expansion port" for a daughter board for:

1=2E An arbitrary waveform generator (the scope lose one channel) 2=2E A 16 bit digital port for analog/digital mixed oscilloscope function (the scope lose one channel) 3=2E To stack multiple board in order to have 4,6 or 8 channel scope.

The overall cost for PCB+(All the components) is about 100=80.

hi,

Davide

Hello Davide, What programming language did you use to develop your applications? regards David Austin

Hi Davide,

What is the architecture of your current software setup? How are you reading from the USB port?

-Le Chaud Lapin-

What about opening a SourceForge project and posting a link to it?

-- Uwe Bonnes snipped-for-privacy@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt

--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

"Davide" schrieb im Newsbeitrag news: snipped-for-privacy@f14g2000cwb.googlegroups.com...

Hello Davide,

I can't do the software, but I am interested to hear more about the hardware features.

Min/Max. Sampling rate: Number of channels: Max. storage per channel: Input ranges: Ext. trigger: Anything else I forgot:

Best regards, Helmut

"Davide" schrieb im Newsbeitrag news: snipped-for-privacy@o13g2000cwo.googlegroups.com...

Hello Davide,

Thanks for this info. I am interested to see the hardware design. Could you please send me the schematics/photos. I promise not to use it commercially.

Best regards, Helmut

Davide said

You could post them in alt.binaries.schematics.electronic

This sounds like an interesting project Davide.

Dear Joerg, The high resolution was intended for the FFT usage. For this feature the 12 bits are useful.

hi,

Davide Joerg ha scritto:

I used the Verilog HDL (Altera MaxplusII/Quartus) for the fpga, the Assembler for the PIC (parallax style macro), and the delphi 5.0 for the applicative. Now I'm developing a DLL for basic command usage in all the languages, but developed in Delphi.

Hi,

Davide

Hi, I'm reading from the USB port using the D2XX functions from FTDI. I installed the driver for the FT245BM chip, and I use the D2XX.DLL module in Delphi for register read/write. Then I developed another DLL (called DSO.DLL) that groups all the medium level functions for oscilloscope usage, for example:

DSO_CONFIGURE(filename:string , force:boolean) configure the ALTERA with the filename.rbf file.... DSO_CHANNEL_SETUP(channel:integer.... DSO_BDT_SET(...) DSO_ACQ_MODE(....) DSO_ACQ_START(...)

All these functions can be used to develop a program directly in Visual Basic, Visual C++, Delphi...

Hi,

Davide

Hello Davide,

With all due respect that isn't going to be nearly enough for today's designs. 20nsec may be ok if there is enough screen resolution. But you don't really need 12 bits for a scope so maybe a trade-off towards higher speed and less bits could be a future thought.

Nice.

Really nice.

Regards, Joerg

Davide I may be able to help with the software if you wish. I've dabbled in building user interface for scopes before. (see

and follow the xProbeScope and 1 bit logic analyzer links.) I'd probably do a web interface using XMLHttpRequest() for your interface, but we can decide on an approach after deciding on the requirements.

Also, if you don't mind being on a Linux site, you are welcome to host your design files on

Bob Smith

Dear Bob, thanks for your offer. I saw the linuxtoys.org website, and this is very interesting. I'm thinking about the functions to include in the applicative. I'm not a software specialist and the "XMLHttpRequest() for your interface..." is not very clear for me....

hi,

Davide

Dear Uwe, I think the project on Sourceforge should be the better choice. I never opened a new project and I don't know how to proceed, but in any case I try....

Hi,

Davide

Hi Davide,

An interesting project, I dont see the memories, how deep are they/ or all sampling are sent to PC in real time? What do you mean "1GSPS equivalent time"? Also I would like to see the schematic, have you posted it somewhere yet?

Regard,

Hi, I used the memories inside the Altera. Each channel has a memory for 1K sample, 512 samples in case of peak to peak sampling. The length of the sweep is 512 samples. I implemented a random sampling using a sub-interpolation for the trigger time. In this way is possible to sample only repetitive signals using an equivalent time of 1ns. I don't know how to post the schematic, I can send this directly to your e-mail, if you want.

hi,

Davide

Hi Helmut, it is possible to fit in the same pcb the ACEX1K50 in place of the

1K30: in this case the memory for each channel is increased to 1.5K samples.

Davide

I've thought about doing something like this myself on and off, but there's a couple of challenges with the approach:

-- Aligning all the paths from one box to the next pretty much implies that you need to generate a common clock somewhere and distribute it to all the individual boxes with some known relation from box to box. If you do restrict people to physically plugging one box into the other (or connecting them only with cables of known lengths that you've provided), this is not difficult.

-- You need to distribute a high speed "trigger" signals to all the boxes so they know when to stop capturing. That's not too hard, but what's harder is that you have to consider whether or not you want every box to be able to trigger or whether you just want to have a specialized "trigger" box... the problem is that, while repetitive random-time sampling is great (with repetitive signals), your trigger circuitry has to operate at the "equivalent time" rate, i.e., much faster than the ADCs themselves.

-- With digital (logic analyzer) boxes, it becomes challenging to start coordinating triggers when the trigger event is something like, "bit pattern

1010xxxx on box #1, then 00xxxx00 on box #3, back to xx0xxxxx on box #1, etc..." (And this is a very simple trigger event compared to what contemporary logic analyzers can do.)

At the end of the day I figured it's be easier just to design one big PCB and populate it differently based on the options a user wants, just like the big boys do. :-) I think there's a huge market out there for a USB-based instrument that implements most of what something like a Tektronix TDS3054 does -- 4 analog channels, 500MHz analog response, 5GSsp. With '3054s going for $10k, if you could profitably sell a USB-based version for, say, $2500, you'd have more orders than you could fill, I imagine!

The Bitscope guys

out of Australia have been quite successful, even though their products are nowhere near as fancy as a TDS3054 (they're basically 100MHz/100Msps with ONE channel and something FAR less with two channels).

---Joel Kolstad