dominant second order created by well known local
large capacitance of a power FET.
a damping factor of 0.7 or so left unadjusted.
minimizing as you can do- right?
His follower is Class B all the way.
That is very typical........
>
The goal is to improve the risetime down to few uS. The original circuit had that "loop gain squasher" resistor from input to ground. I got the impression here that that was considered to be poor practice.
And this is adjusted by adding one or more r/c feeback paths?
Yes, I have the op-amp driving an emitter follower which drives the bjt pair which drives the gate of the powerfet. To reduce the deadband I've tried a Schottky diode at the emitter of the emitter follower.
There is usually a better way to deal with excess gain. But where the noise and offset problems of your "loop gain squasher" are tolerable, it may be the simplest and therefor best solution. I would chuck "no loop gain squashers" from your rules of thumb collection.
For the speed you mention, a sufficiently fast op-amp is the simplest adjustment. Dealing with op-amp poles near where you want your loop response will be a PITA.
If the BJTs conduct little current during settling, then the stage output impedance is going all over the place, along with its delay. This will complicate the task of compensating the loop for fast response. Issues like this are why I suggested you post the schematic, so we need not guess what you have.
-- --Larry Brasfield email: donotspam_larry_brasfield@hotmail.com Above views may belong only to me.
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