Unity gain buffer amplifier to lower impedance

Larry Brasfield wrote: [...snip pseudo-intellectual dodging and backpedaling...]

You picked the *wrong* part both for the bandwidth and the drive requirements- you are a sorry-sack-of-sh_it loser who doesn't know his ass from a hole in the ground...

In article , Larry Brasfield wrote: [...]

Yes, the 90 was an error, I intended 60 as the band in which there was a peaking. The 90 was part of another though I removed from the post.

It was a general claim I was making and with the correction of 60 vs 90, it is correct.

Take a look at the 10th page in the upper left corner. I think it is obvious that the op-amp must have zeros.

It is the increase in gain at the gain cross over frequency, increasing the amplitude of a selected harmonic that is at issue.

Warning: I expect you've just opened yourself up to another FB flogging.

[...]

Your "realistic" would be called "sloppy beyond all reason" in the industry I work in. In the "audio" business, and a lot of other consumer stuff, no-one will ever know if 10% of the units don't really meet spec.

In that case you need to look again and much more carefully this time. The noise at 3KHz is just about 1nV/sqrt(Hz) at 300KHz it is about 3 times this figure.

I always assume that the parts the salesperson brings as samples are about the best ones they make. I've been proven wrong on this twice. In one case the "salesmans sample" was actually defective and had obviously never been tested.

Much less than 50 Ohms would be needed to improve the stability.

I spoke at some length with the Linear designer (I think it was actually the guy who did it), when I discovered the effect. He confirmed that it is real and due to the fact the first stage is low noise but has a limited bandwidth. As the gain in the first stage falls, the following stage's noise starts to matter. The second stage runs at a much lower current and is much noisier than the first. This explains most of the noise character.

The fact that the LT1028 has a couple of zeros in its transfer function to make it stable for gains over 3, provides an added bit of complexity. These zeros work to boost the high frequency noise as they boost the high frequency gain. I think this is the reason for the peak at about 500KHz and then a bit of a tapper down from there.

In article , Larry Brasfield wrote: [...]

No-one where I work would use a typical noise or distortion spec as what to expect in the design. If the typical is 10 times better than the circuit needs, the typical would be used as an indication but there would be nervousness.

Like I said "it would be *called* sloppy". I have engaged in some such name calling directly to our customer base when we discovered that the other guys had a spec that only worked as a typical.

Oh! I see nothing in the bias current cancellation that would make the increase I observed.

In article , Jim Thompson wrote: [... LT1028 ..]

(see other reply)

The peak was well below the point where the peak would be expected for a compensation issue. Also I was running the part at a gain over 50 and it is stable over 3 or so. I don't think there was an issue with the loop peaking that has been the main topic in this thread lately.

Also the component values near the LT1028 were all quite low impedances. It mostly saw a reactive impedance.

In article , Jim Thompson wrote: [...]

The quote from memory: "Its a wonder we got it to work at all".

"Ken Smith" wrote in message news:d2q2et$65c$ snipped-for-privacy@blue.rahul.net...

If you are using an op-amp in a position where noise is important, there are plenty of such devices with noise guaranteed. For many applications, it would be smart to use one them in that case. I am not making any claim to the contrary.

Distortion is a more interesting spec. It hardly ever makes an appearance in the min or max datasheet columns. Yet the vast majority of op-amp usages would fail if the device distortion were to become large enough. People who use those parts are relying on an unspecified parameter whether they know or acknowledge it.

Must be a strange business where people get away with not meeting an important spec for any length of time.

Looking at the datasheet, I see that the bump is shown for voltage noise, which cannot be affected by that bias current cancellation circuit (which only feeds current back into the input). I remember looking at that and thinking it was kind of a strange thing, adding current noise into the input to counter bias current which is hardly much of an issue when the part is used with low resistances at the input, as it has to be to get its decent noise performance.

I read in sci.electronics.design that Larry Brasfield wrote (in ) about 'Unity gain buffer amplifier to lower impedance', on Mon, 4 Apr 2005:

It's called 'government', and they wrote the spec themselves.

I have a question on this general topic, but certainly for a lower bandwidth. I'm using a complementary bjt pair to aid an op-amp to drive the gate of a powerfet. The feedback is from a sense resistor measuring the powerfet current. My problem is overshoot. What are the recommended methods to avoid overshoot?

Thanks,

Dave

"Ken Smith" wrote in message news:d31mt2$3k9$ snipped-for-privacy@blue.rahul.net...

My comment, made in response to yours, where "[t]he noise" was 3 times worse at 300 KHz than at 3 KHz, was a mistake, based on a 13+ year old memory of a strange circuit for a part whose noise performance was its chief claim to fame. Without knowing that the phenomenon you mentioned was, in fact, only voltage noise, I surmised, *incorrectly* and *erroneously*, that the bias cancellation had brought it about. So, if you are one of those who likes to track such things, chalk one more up in the "Larry was wrong" column.

Reactive doesn't help with respect to bias current noise. That is largely uncorrelated to the input voltage noise, so the magnitude of the impedance through which the bias current flows is all that matters w.r.t. total noise.

Minimize phase delay in your post-op-amp boost amplifier. Get its gain and delay to be stable and predictable. (Optional, depending on desired response speed: Compensate the boost-amp + FET pole(s) with similar zero(s) in the op-amp controller.) Control the loop gain to maintain phase margin in excess of about 60 degrees. For no overshoot, keep the phase margin above 75 degrees.

Depending on the design of your boost-amp, deadband might contribute to overshoot.

You may want to post your circuit with a request for improvements. Among all the responses, some useful ones may be found.

You're welcome.

In article , Larry Brasfield wrote: [...]

Virtually for everything sold to the unwashed masses has a certain percentage of the shipped product that does not meet the important specs. If it is bad enough that the user notices and raises a fuss, the product will be repaired or replaced.

So are you now saying that the comment about the bias compensation being related to the noise voltage spec was an error?

In my application of the LT1028, the raw bias current of the input transistor could indeed have been a serious cause for error. As I noted elsewhere, the input of the LT1028 saw a low valued reactive impedance at the operating frequency.

More generalistic garbage with no backbone- overshoot is a well-defined function of phase margin when the amplifier is a dominant second order created by well known local feedback swamping techniques. It has nothing to with "Minimize phase delay in your post-op-amp boost amplifier..." which may be impractical as hell when dealing with the large capacitance of a power FET.

In article , Larry Brasfield wrote: [...]

I take no joy in proving people wrong. I just didn't like what appeared to be conflicting statements. There is nothing wrong with being wrong from time to time. Letting misinformation remain in place can harm the less experienced.

I was refering to the DC bias current in my statement. The DC bias of an uncorrected LT1028 could be enough to introduce a DC error that would have caused me troubles. Imagine the case of a capacitive transducer and you will see what I mean.

I assume it is basically the circuit topology shown below. The circuit shown is not likely to work in real life.

ASCII Art: Vcc ! !/ ---! ! !\e ------!+\ ! ! !!----- ! >------+ +-----! --!-/ ! ! !!-- ! ! !/e ! ! ---! ! ! !\ ! ! ! ! ! GND ! ! ! ----------------------------+ ! \ / \ / ! GND

First off, the op-amp is working as a unity gain buffer with some extra phase shift added inside the feedback loop.

Normally to make this circuit stable feedback is taken directly from the output of the op-amp capacitively back to the inverting input. This reduces the gain of the system and also makes the op-amp appear to have nearly exactly 90 degrees of phase shift. If the rest of the circuit has less than about 90 degrees the circuit will not oscillate.

There are some gotchas in this method. One of the biggest is the fact that the set point comes in on the non-inverting input of the op-amp and thus arrives quickly at its output. If you are moving the set point, this can be a major source of overshoot. A very simple way to fix this is to place an RC lowpass on the setpoint input.

Making the op-amp appear to have 90 degrees of lag also means that 90 degrees is the most phase margin you could ever have in the overall system. The MOSFET's input capacitance is going to add a bunch more phase lag to the system so you are likely to end up with some peaking and overshooting. One way to reduce this is to place a resistor in series with the capacitor providing the feedback at the op-amp.

Using an RC local feedback adds a zero to the system. When this zero is below the gain cross over frequency, you can use it to improve the phase margin. In most situations, it is simply the phase margin of a control loop that determines the overshoot, peaking and ringing in a closed loop system. If you want no overshoot you will need to have a large phase margin. Unless the system is something contrived, a phase margin or 80 degrees is enough to have no overshoot.

"Ken Smith" wrote in message news:d32auq$2tt$ snipped-for-privacy@blue.rahul.net...

Please accept my apology for suggesting you might be among that juvenile score-keeping set. You've done nothing I recall to warrant that suggestion. My reaction was a spillover from what I've seen others do here, not personally directed at you.

I agree that clearly resolving error has value.

dominant second order created by well known local

Thanks for confirming my advice regarding phase margin.

large capacitance of a power FET.

With minimal and reasonable reading between the OP's lines, one can infer that he has overshoot because he wanted more speed than could be achieved by merely turning loop gain down far enough, or by eliminating his boost amp and turning down loop gain.

You statement that it may be impractical to minimize phase delay in the boost amp is naive. To minimize does not have to mean "eliminate", or even "reduce to a negligible level". It simply means "make as small as practical in light of other constraints". Doing that will help acheive the OP's stated and inferrable goals.

It is likely that the gate capacitance of the FET will continue to be significant after its effect has been minimized. That is why I mentioned compensating for it, optionally, depending on the speed requirement.

....

dominant second order created by well known local

large capacitance of a power FET.

That would be one reason. My point goes to "Why has the OP let this overshoot condition exist when it is so readily cured by increasing a feedback capacitor?" I doubt he came here just to be told to slow his circuit.

a damping factor of 0.7 or so left unadjusted.

At this point, I see no reason to affirm or deny the idea that the op-amp response has to be a signficant part of the current control loop response. Depending on what speed the OP's application requires, and how big that FET is, the op-amp poles could be either way out of the picture or near the main loop poles.

minimizing as you can do- right?

Hardly. Even if a single stage follower was ordained, there would be issues with how it was biased affecting the phase lag under settling conditions when the FET gate current is minimal. Depending on the amount of quiescent power that could be burned, this could be a difficult issue, or one requiring a compensation scheme that adapted to lag in the follower.

There is certainly room for amusement here since the OP has not shown enough interest to respond in any way.

dominant second order created by well known local

large capacitance of a power FET.

Nope- the OP has overshoot because his circuit is undercompensated.

Not really- he still has the opamp to contend with and most of these will have a damping factor of 0.7 or so left unadjusted.

Well- driving it with a complementary emitter follower is about as much minimizing as you can do- right?

Heheh-