mosfet switching time vs temperature

Capacitance probably doesn't change. Threshold will though. The hottest will switch on sooner due to reduced Vgs(th).

Just how slowly are you switching them that you're concerned about thermal effects in parallel? 10us+? Doesn't matter, switching mode FETs parallel good anyway.

And don't you mean decrease, anyway?

Tim

-- Deep Friar: a very philosophical monk. Website:

Hi,

Nope I meant increase. The fastest FET will absorb more of the switching losses than the slower FETs in parallel with it, and to a lesser extent during the extra few nanoseconds it might be on, it is absorbing all the losses that would otherwise be spread equally over the fets once they are all turned on. For say 5 parallel fets, this could become significant if the same FET is always turning on first. From what you said about V(gs) decreasing with temperature, it seems like it could be a problem for parallel FETs. It would be good to use a delay to allow one FET to turn on faster than the others, and for each switch transition, change the FET that turns on first so that the switching losses are evenly distributed. That circuit would require individual gate drivers per FET instead of the simpler parallel resistors and single gate drive.

cheers, Jamie

You mean switches slower, thereby having a longer transition time, resulting in more power dissipation?

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The faster FET has lower switching loss, but has marginally more (a few nS' worth) conduction loss, right?

Vgs(th) drops a little with temp, but that hardly matters because you're driving the things with a hard edge anyway.

And FETs share conduction losses fine--the hotter FET increases its Rds(on), cutting its current, and its paralleled buddies--all seeing the same voltage--carry more, spreading out the load.

Switching losses are usually fairly trivial these days anyhow, aren't they? If switching losses predominate, you're paying for too big of a FET.

-- Cheers, James Arthur

Mosfets get slower when they get hotter. You can see this in common cmos logic... HC, FPGAs, whetever: prop delay increases with temperature. For HC, it's around 2% per degree C. FPGAs are a little better, typically maybe 1%, possibly because a lot of the delay is caused by routing and not just fets.

Paralleled mosfets seem to work fine, at least in switchmode.

John

Hi,

For the parallel FETs, the faster FET has more switching loss than the slower switching ones, since the other FETs may switch for free, due to zero voltage switching (ZVS) once the first FET has turned on the drain voltage will be near 0V (for n channel lowside FET switching applications etc)

cheers, Jamie

For fets driving the same drain node, the drain of the part with the lowest threshold voltage will drive the Cdg of all paralleled parts - potentially acting against their enhancement.

If the drain voltage doesn't fall immediately - due to rectifier stored charge or other factors, all gates will likely be enhanced by the drive before the drain voltage dv/dt becomes signifigant.

RL

Hi,

Switching faster is good overall, ie. all the parallel FETs switching at an average time of 10ns is better than an average time of 100ns, but once they all average 10ns, it may be better that the fastest FET in the group, ie. one with a 9ns switching time, and thus absorbing more of the switching losses perhaps, would switch slower once it heated up.

cheers, Jamie

That went a mile over my head :)

cheers, Jamie

"John Larkin" wrote in message news: snipped-for-privacy@4ax.com...

That's probably due to Rds(on) increasing. Low voltage FETs don't increase much, you can buy 20-30Vds(max) FETs that are

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I don't think it's a problem generally, but some math is in order. Just figure the expected spread in FET thresholds, the slew rate of the drive, and you can calculate the spread in switching speeds and then instantaneous dissipations.

Drive them hard and fast and it probably won't matter. Or drive them in a controlled-rise manner so they're all guaranteed to pitch in and it probably doesn't matter either.

It's self-equalizing in that the most eager FET taking more than its share of the switching hit slows down as it heats, and the rds(on) of the FET with the greater conduction loss increases too, spreading the load.

-- Cheers, James Arthur