Transistor Veb rating... plus Patent Update

I wouldn't place much faith in them until doing the real-world tests. The kinds of parameters you're interested in are exactly the same ones so many manufacturers get completely wrong in the macromodels they supply. I'm not suggesting bench tests of your entire circuit concept at this stage, rather I'm suggesting a simple test rig specifically designed to evaluate the critical IGBT parameters, to test the models.

DNA, if I may ask, what's the deal with your "patent application"? I mean, where's the prior-art research and references? Where're the claims? Aren't those things required in patents over there?

Yes that is the intent and nub of your idea.

But I still suggest that the reverse pulse across the IGBT can only be applied whilst the MOSFET inside the IGBT is ON. Only in this way is the base of the pnp safely held at a known voltage (0V).

If the internal MOSFET is OFF then the drain of that MOSFET could (will?) be driven negative, with unpredictable results inside the IGBT.... but see below, IRG4BC40K.

It would seem prudent to only turn the IGBT OFF as the reverse pulse comes up and crosses 0V again.

Are there any manufacturers figures of maximum reverse voltage or plots of reverse current?

A quick google has just answered that.... the IRG4BC40K has a V(BR)ECS breakdown of 18V, with a VGE of 0V, and IC of -1A.

Isn't V(BR)ECS the answer to your original question?

I will have to look at what I 'think' the internal structure is like again but I think the mosfet body-source diode is still present, it forms a parasitic thyristor with the PNP, so it should be available for conduction with the mosfet nominally off. In my present ciruit I am overlapping the drives so the internal mosfet is on as the reverse bias is applied.

You are right about V(BR)ECS, silly me really. ST quotes 20V and I have seen other references to the fact that it is dependent on the processing of one of the doping layers so it could be made bigger, probably at the expense of other parameters though.

The people who were looking at it but said no do not quote a figure for their devices. I'm assuming that's one of the reasons for saying no....

I'll be updating the second wubpage later on today to include more words and simulation results.

Cheers

DNA

Yes, me neither. I will have jumped the gun but, for me, there is enough of a feelgood factor about it along with a little bit of knowledge to have some confidence.

As to trying it out... Unfortunately I don't have the resources to do it. I did suggest to the people who were looking at it that they should and would have to verify things for themselves but the 'expert' said he didn't have the resources either?????

I don't quite understand that one since they must have to qualify the devices they produce and it should be simple to modify their own test rig. It's either something or something or something and probably buried in the political side of things.

The application is provisional. In the UK you are allowed to file a description to gain a priority date. Drawings, Claims, and Abstract can follow later as long as it is within one year of the filing date.... The same time period also applies to filing in other countries.

You are not allowed to add technical detail over and above that in the original filing. However it is possible to either re-file or file something else whilst claiming the original priority date if you wish to either make cosmetic changes or additional detail is added.

I'm not sure about a requirement for Prior Art but if it adds no technical detail to the invention itself then all it is is background.

Don't quote me on the above. I am kind of a novice at this.

As you would say....

Thanks

DNA

OK, the second page with a 'proper' PFC model and results is sort of finished and up.

First page

Second page

Have fun

DNA

Isn't that assuming a "simple" model of just a mosfet and a pnp?

If you take account of the other parasitic npn transitor in there, there is a diode (cb junction of a pnp) between the base of the pnp and it's collector (emitter of the device). This will hold the base of the pnp at

I think Genome is onto something. But I can't help thinking the implementtion of it is a bit complex and there might be a much simpler method.

...there is a diode (cb junction of an NPN) between

That seems sensible enough, and was my first impulse before deciding advantage might be gained from a FET's fast turn-on too.

At bottom, I'm unsure of the IGBT's real switching times. The Siemens datasheet for the BSM50GB120 used in this simulation shows ~65nS turn-off, but they don't define "turn-off," i.e. i(c) = falls to ?? % of i(c)(on). The simulation (Fig. 4a) shows a ripping i(c) edge followed by a lossy ~1uS i(c) "tail" at Vce=max.

I assume the tail exists, otherwise the interest in it wouldn't.

Genome's intended gizmo still has merit--it would be faster, if he can make it work.

Nice link -- thanks.

James Arthur