TINA

s being sold, usually by people with an inflated idea of their own competen ce.

t exactly the usual way of doing business. Being economical with the truth about the relative merits of your mousetrap does seem to be more popular - for one thing you don't have spend as much time finding out about competiti ve mousetraps.

Larkin sells most of his products to government entities, so he's another o ne on welfare. More and more Obama's statement about "you didn't build that " is ringing so true, and that's what has made these people so mad.

I wanted to evaluate transient line and load regulation, and tune the loop dynamics, which are not things that I'd want to (or even be able to) do analytically. The dump/min load resistor improved the loop by keeping the fet current from having an infinite operating range.

LT Spice is easy to use, free, and works very well for me. The built-in documentation is mediocre, but the program is so popular that there are tons of help-ey things online, some of them very good. You can google most any obscure issue.

I use LT Sice sims as project documentation, too. I'll save a well-commented LT schematic in a project file for future reference about what we did and why.

It's a great tool, and Linear did a great thing by making it public, for free.

I did find one crash bug and emailed Mike about it. He was traveling but got back to me right away, thanked me a couple of times, and fixed it in the next release. I had the opposite experience with EWB.

My biggest customers, at present, are people who make jet engines, and semiconductor fab gear, and analytical instruments, all public companies. We haven't had a big government job since NIF, many years ago.

The problem with government biz is that it's usually project-based, which makes it a big spike of sales that doesn't last. Hell of a way to run a company.

I do admit, gratefully, that my company, and its technology, got an early boost from a couple of the US National Labs. A guy at Los Alamos deliberately forced business on us so he'd have an alternate to buying from LeCroy.

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The original remark was about LTSpice, too many quirks (by way of really o dd DC convergence issues), really bad documentation, and the results are su spect. And so what if it's free, it's more trouble than it's worth.

You've been suckered into the wishful thinking trap if you think the SPICE transient sims are even close to reality.

There are plenty of low cost versions of SPICE that are almost free, and fu lly debugged. What the heck is EWB? Was that some kluge Tango evolved into or something as an aside?

EWB = Electronics Workbench. Formerly Multisim. Apparently Miltisim again. AKA POS.

National Instruments owns it now.

It was Multisim when I bought it, with guaranteed lifetime updates. So they changed the name to EWB to renege on that.

I can't really let that one go by. If the models and system are modelled correctly, Spice is nuts on.

There is a big distinction between board and ic design. 10,000 analog transistor count ics are routinely designed entirely in spice, with the match between simulation and reality, essentially perfect within design tolerances.

For those here not doing ic design, it is worth noting what is not actually open to debate. The ONLY way 10,000's of analog/mixed mode designs with billions actual ic manufactured units are designed today, is purely in the virtual universe. It would be outrageously expensive to do it any other way.

Typical complex analog/mixed mode ics have 100s to 10000s of individual blocks, e.g. PLL, LDO, OSC, LNA, Charge pumps etc. The bulk of the individual blocks are never even tested individually, they are simply not accessible.

Its impossible to design an iPhone on the bench. Its that simple.

Kevin Aylward B.Sc.

It sure works for me. I verify or tweak things in sim, build them, and they work.

One great thing Spice does is train my instincts. I can learn causalities of a complex circuit, so that I can better understand what's going on when I actually build it. Typing is sure better than iterating 0603 parts with a soldering iron.

Do you think that anyone ever simulated a whole iPhone, RF through touchscreen? I sort of doubt that. I do suspect that it was breadboarded.

We do board-level design and we only simulate small sections of an overall design. Some product designs involve no simulation at all.

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Couldn't be breadboarded. If you saw several of the internals analysis videos on YouTube you would know why as well.

Somebody simulated each and every IC in the design, but no one company simulated all of them at the transistor level.

There are tools to simulate at the block level (meta models of each IC) using extra-detailed datasheets that major manufacturers can get. You can bet that Apple did do a simulation of the whole phone at that level. And they simulated every basic function and standard application. Meanwhile they laid it out did all the thermal management, wirebond placement and base PWB. It is a giant hybrid really.

It sure works for me. I verify or tweak things in sim, build them, and they work.

One great thing Spice does is train my instincts. I can learn causalities of a complex circuit, so that I can better understand what's going on when I actually build it. Typing is sure better than iterating 0603 parts with a soldering iron.

Yes. Its done by constructing behavioural models.

For example, I did the analog of a 64 channel printer driver asic. It had around 10,000 analog transisters. A colleague did the 100k digital control all in vhdl.

It had high speed dacs, analog muxs, pgas, controlled ramps etc. about 8 deep hierarchy, and maybe 100+ analog blocks. A full chip sim would have taken days to run. Around 30 mins for the behavioural version.

At the lowest level block, for each block, I created a behaviour model in parallel with the real schematic. The behavioural and schematic are made to match pin for pin. This way all of the 10,000s of routing connections can be verified. In Cadence, a "view switch" is set up so that either the real schematic or behavioural is run. Quite simple models can be used. The purpose is to check functionality, assuming the real blocks have been thoroughly simulated. For example, an ideal resistive relay can be used in the power supplies of each block, with turn on setpoint set by the supply itself.

One other approach is to do the behaviour in big functional VerilogA. I think this is very misguided. It doesn't check the actual chip! VerilogA is a solution looking for a problem in my view

Kevin Aylward B.Sc.

I can't believe that Apple simulated "every basic function and standard application" of an iPhone. It wouldn't run at a millionth of real time. Probably not a billionth. Why simulate the RF front end and the power supplies and an ARM CPU and an LCD and a touchpad to develop apps?

Within reason! Sure, you don't need to have a full uP driving the analog. Its control still needs to be fully verified though, say with custom verilog stubs mimicking what the uP would have done.

And I also said behavioural!

Big chunks of the RF chain will be simulated at various levels of abstraction. RF chains absolutely need to be simulated with their power supplies in detail.

Analog Verification is a big bottleneck today for todays SOC , but it needs to be done. Mask sets can get the the $1M a pop. Chips need to work first time.

Kevin Aylward

Like you.

Like you, no doubt.

John - Thank you for supporting LTSpice. I, too, find in an invaluable tool. It is a relief to see someone else support it earnestly.

JohnS

So, you don't know how to use it.

I know lots of people like you, always putting their foot in their mouths.

Thank you for demonstrating that most people don't change.

Jamie