this is getting crazy

Hello James,

Atmel is certainly more competitive in pricing than TI. But from what I have seen there is one problem. In power-down they consume next to nothing. However, many of my circuits do not have a power switch and must still constantly monitor some parameters to detect when they should turn themselves on. A few uA are ok but not the 250uA that Atmel says.

Regards, Joerg

Indeed. "C" for "Clear" would be my guess.

And thats exactly what they look like. Quite pretty actually :)

To be honest, I am absolutely astounded that they made that part. So far, we have only made 20-30 pre-production prototypes. Admittedly they each have 121 photodiodes. But the projected sales volume is tens of thousands per annum, so thats millions of photodiodes. Hey, this is almost as neat as building LED video screens :)

But thats not so cool.

check this out:

Aside from the fact I get paid, its heart-warming to design something thats truly helpful. These guys went from 2 to 20 wpm with LOMAK. Not that any of that is my doing, I just designed the circuitry, the really clever stuff is how the user interface works. Its the brainchild of a guy who worked as a sparky at a facility for disabled people, and was disgusted at the primitive human-computer interfaces available (mostly a stick held in the mouth). He then went to tech and studied electronics, so as to built a proof-of-concept prototype. A very clever man.

Cheers Terry

Way back in the original Fairchild daze of digital, analog & discretes, Fairchild made a photodiode that was orders of magnitude more sensitive than the standard lens-at-end-of-can transistor type. The emitter was as dinky as possible, and off in a corner so that even the wirebond would not shadow the active base-collector junction. The processing was tuned to increase the photon capture. Two versions were made: one with a flat clear light entry, and the other with a clear lens. All plastic / epoxy construction (no special glues to hold glass to metal as in the standard types). FPT100 and FPT101 if i remember correctly.

FTP110 was the planar version. I used it to look at a glass tube carrying dirty water. The water+tube formed a very nice cylindrical lens between the LED and the photocell.

Howdy Joerg, I've not used either part, but reading the data sheets, they don't appear that much different w.r.t. power consumption. Both draw in the neighborhood of 300uA @ 2.2v and 1MHz.

Lower consumption is available with either device by o turning off unused peripherals, o switching to slower clock rates, o sleeping with wake-on-event, o or sleeping with wake-on-watchdog.

Wake-on-edge-detect is especially useful.

Once you slow down and start turning things off, the draw for both parts gets quite low.

James

Joerg, It seems your wishlist has grown !!

You're right, I don't think the ATTiny13 does all you ask. It does, however, have an 8-bit clock prescaler, allowing one to switch frequencies. Figure 64 of the datasheet indicates a draw of about 30uA @ 100KHz and Vdd=1.8v. One could prescale the internal 4.8 MHz RC oscillator to as low as 18.75 KHz.

Wakeup time is selectable, as fast as 6 clocks.

Cheers, James

Hello James,

Yes, but the TI part has two oscillators and you can run it on the 32k crystal while the other oscillator is turned off. You can wake it up in less than 10usec, do some stuff and send it to sleep again. With the 32k oscillator alone it draws just a few uA. I haven't seen any other micro that can do that (and has 16 bit math capabilities...).

That isn't always possible. In some of my designs several parameters have to be watched. It can be done during a wake-up time but not if the oscillator takes the usual few 10msec to yawn and stretch. Better would be not to have to go dormant. With the MSP you don't have to, plus it can keep realtime without the expense of another chip. But then again they are expensive which rules them out for many designs.

I am surprised TI hasn't yet come out with a minimalist device that features a simple ADC. You can't really use slope because then you need to run the comparator which guzzles quite a bit of power.

Regards, Joerg

Hello James,

Well, what can I say, I am married to a marketeer ;-)

If that scales down CMOS fashion plus some quiescent current it should be a little over 10uA at 32kHz. That's still high for battery operation but might just be good enough.

This is nice. So the device should certainly be viable in cases where a realtime clock isn't required.

Regards, Joerg

Our trend is to one huge, 600-900 ball, BGA connected to a lot of other parts: level shifters, ADCs, DACs, rams. Since none of the other parts have JTAG, there's no point in using it in the FPGA.

What surprised me is that my assembly people prefer BGAs to TSOP-type parts, and get much better yields... 100% so far.

John

No! We told our layout guy what things needed to be connected to which FPGAs, told him which pins were unassigned i/os, which ram pins he could scramble, and let him optimize the routing. So most of the serious stuff is clean, via-free, spiffy-flowing layer 1 traces. Then we back-annotate the schematic and run a perl script that crunches the PADS netlist and gens Xilinx pin constraint files.

Oh, I do believe it.

Placement, placement, placement.

As I said, we let our layout guy do it. He does an excellent job, even though he doesn't understand the functionality at all. We review it along the way to make sure it will be electrically nice.

Right.

The thing that doesn't work is the "throw it over the wall" method you see in big companies or with outside contractors. While a serious board is being laid out, we work with our layout guy constantly, and we discuss things, and we often change the design to help him make a beautiful layout. 16-bit bus too nasty? OK, we can live with 8.

John

I feel your pain. Did you use an autorouter on this? We have given up on autorouters. Even Specctra can't manage to do a decent job on our dense boards, and managing signal integrity after autorouting is a nightmare. So now we manually route boards, even with 1,000+ components. Believe it or not, it takes us less time and it costs us less in the long run.

We have found that the key to a (relatively) painless layout is lots of planning prior to routing.

I always select pinouts on CPLDs, FPGAs, resistor networks and connectors (where possible) to make the layout as easy as possible. It takes time to do this, but this time is saved during layout. This approach provides shorter signals with fewer crossovers, which is always a good thing.

I try to select component packages that will provide for the best physical flow of signals on the board. In this respect a larger component package may provide better real estate utilization and/or signal flow than a smaller package. Thinking about all of this stuff during the schematic phase pays off huge dividends later.

The three most important things about real estate are location, location and location. This applies to circuit boards too. I group parts in OrCAD to make the initial placement easier. For critical groups we may even route and lock it prior to placing other components. We spend lots of time on the group and component placement. A well placed component is an easy to route component.

I group nets in OrCAD so that these can be easily seen during routing. Also, I prepare a list of critical nets (clocks, strobes, resets, diff pairs, etc.) so that these can be properly managed.

With this approach we save time on design, save layer count, and reduce the risk of having another board spin because of signal integrity problems.

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Greg Neff VP Engineering

For ground lugs (mandatory) we use these turrets:

We don't bother swaging them, we just solder them like any other part.

Where space permits, we use mictor connector footprints (compatible with Agilent logic analyzer probes) for active signals. These are normally not installed, but easily added for debug purposes.

We implement JTAG boundary scan chains (mandatory) so that we can debug connection problems with BGAs and other high pin count components.

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Greg Neff VP Engineering

Yup. Our only problems have been BGAs with integrated copper plates. These provide very low thermal resistance when running, but make things interesting when developing a reflow profile. We have had problems at two extremes, with a 9 pin Fairchild MOSFET and with a 480 pin Freescale processor. The copper also means that you need a decent X-ray machine for inspection. We have had no trouble with plastic packages, including 0.8mm pitch parts.

We only use BGA on the primary side, and other packages on the secondary side. As far as I know we can't put BGA on both sides of the same board. Have you seen anyone using BGA on both sides?

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Greg Neff VP Engineering

I don't do the layout myself. I could if I had to, but I don't have time. Glenn (our layout artist) makes it look easy and is better at it than I would be. Once upon a time I would spend weeks slouched over a light table with blue and red tape, so Glenn (who used to do the same thing) respects my input and direction. I do spend lots of time planning the layout so he doesn't have to guess what I need. I also have the layout software on my system so that I can review the progress on an ongoing basis. At critical points I stand looking over Glenn's shoulder. This would drive lots of people nuts, but Glenn puts up with it. If needed I forward annotate changes from the schematic to the layout, and at the end we double-check the layout against the schematic netlist.

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Greg Neff VP Engineering

Treasure your layout guy. He's a rare find IMO. I'm firmly in Gregs camp, I do the layouts myself (hey, I get paid by the hour :) because it ends up faster than trying to explain things to the layout guy. I've had some terrible experiences in the past :(

I also do a crosstalk analysis, pre- and post-layout. Then measure it on an un-populated PCB, just to be sure. Peer reviews (harder as there is only me) to catch all the deliberate mistakes - I have a long, long list of things to look for, perhaps 20-30 per component type, as well as a list of all fuckups I have ever made or been witness to, to ensure they dont sneak back in. That way, I get to spend all of my debug time working on new mistakes, rather than re-hashing past c*ck-ups. And when a design is finished, a lessons-learned review pops those mistakes into my peer-review checklist - eg I will never use another opamp without measuring its PSRR, having been bitten badly by a TL064, which had

One day when I'm rich and famous, I'll get to use gazillion pin BGAs. We recently did EMC compliance testing on a PCB with a 55W planar smps, micro & CPLD. lovely ground planes (no slots at all), back-terminated clock line (15mm long), etc. the smps was quiet, but the TQFP144 CPLD package spewed out bucketloads of noise - confirmed by shielding the package, which fixed it. not a very large die, nice long bond wires. Luckily its expensive and hard to get, too :)

Cheers Terry

Seek help.