I'm trying to figure out if I can run the dsPIC33 at the maximum 40MIPS and use the PWM output to clock an external ADC without introducing the phase noise(into the ADC) associated with the internal clock PLL. Is there a way to have the dsPIC processor use the clock PLL but have the PWM circuitry directly referenced to the external clock?
Thomas
FWIW not very long ago I had to wrestle with the phase noise of the signals generated by BlackFin DSP. You won't find any phase noise specs on MCU generated signals, as those noises are strongly correlated with the activities of MCU. You can expect jitter ballpark ~50..100pS. It doesn't matter much if you are using or not using internal PLL. So, if that kind of jitter is important for your application, you have to reclock the MCU generated signal into external latch, or use completely different clock chain.
Vladimir Vassilevsky DSP and Mixed Signal Design Consultant
Apparently the mechanism on this stems from internal noise affecting the thresholds of the gates -- so even (as you say) with a perfectly stable clock you'll still see phase noise.
I hadn't thought of resampling the output -- I'll have to remember that.
-- www.wescottdesign.com
There is significant coupling inside the chip; crap flies by stray capacitances and supply rails. Nobody can tell for sure how big are those effects.
The most fancy solution I thought of was negative feedback of jitter from MCU output to MCU incoming clock. Jitter can be measured against clean external clock; so the whole thing is a sort of PLL.
VLV
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.