ADC Converters (General Clocking Question)

NXP makes 8051 derivatives to 33MHz.

Why not, many microcontrollers run at 16Mhz or above. For example. AVRs.

Why can't you drive both with the same crystal/oscillator?

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1 / 33 MHz =3D 0.03 uS

If it takes 12 osc. clocks to make a single instruction cycle, then each machine cycle would be: (12) (0.03uS) =3D 0.36 uS (12-clock cycles were/are used in the earlier 8051 devices)

On clock-doubled parts, if it takes 6 osc. clocks to make a single instruction cycle, then each machine cycle would be: (6) (0.03uS) =3D 0.18 uS

And keep in mind that some opcodes require more than one machine cycle to execute. But, taking the best case (6-cycle), 1 / 0.18 uS is still only 5.5 MHz, and that's not nearly fast enough to clock 256 x 44.1 kHz (i.e.,

11.289 MHz)

A single-, or two- clock 8051 derivative might do it. I've not played with these before (if they exist)? Still wouldn't give much time to do much of anything else. Maybe a couple dozen op-codes in between required ADC strobes. (??) Couldn't screw around in coding, that's for sure. Would probably have to be assembler -- which is fine for this project.

-mpm

ext -

Lightbulb on!! Maybe. I never thought about using an external oscillator to drive both the microcontroller and the ADC. That seems like it should work. Just need to look at how to synchronize the two, which I can probably do by timing the ADC reset...?

For some reason, I was thinking (lazy?) that I had to use the internal

8051 osc. You get so used to trying to save parts costs, I'd forgotten you could use external clocks with many 8051's... Duh!!

Thanks for the insight!!

-mpm

Your main problem is not the clock generation per se, but how to connect the I2S slave bus of the ADC to the microcontroller SPI port. The clocks can be generated either by timer output compares or by an external hardware counter. Master clock could be the CPU crystal.

But what are you going to do with the ~200KB/s traffic of the ADC using the miserable 8051? You need better CPU, something like BlackFin would be appropriate.

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

part:

Nowadays any old 8051 should be able to run at around 11.3MHz. Just make sure that your desired clock frequency does not mess up other functions such as serial port timing.

Even if you use the crystal on the internal oscillator you can often (gently) tap off the OSCOUT side of it and, if need be, buffer with a

74HC chip. Or look if a port pin can pipe out the master clock directly. [...]

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Why not? You can use a separate oscillator to generate all of the clocks. and dump the data to an external shift register and data latch. your data then appears at a 44.1 khz rate, 4 bytes. you have 22.6 us to read it.

If you do not need the oversampling then why not sample at a much lower rate? i.e., you could get down with 1/256 and still have cd quality. It looks to be a pure serial output so you could simply add

256 samples and average or ignore all but one. In any case you would still have to supply a clock to the ADC but your computation could use a much lower sampling than what the adc does. The oversampling is there to provide better filtering and processing but if you don't need it then no reason to make it more complex. I would think you could find a better adc that could have a programmable oversampling other than 256, 384 or 512.

Thats 22.6 uSec for all 4 bytes.

Whats the fastest transfer loop that a 8051 ( even a 100Mhz Silabs ) chip can transfer to memory ??

Where will the 8051 ( even with 64K of External Memory ) going to put all those bytes ??

After "recording" the source, where will the 8051 put it for safe storage ?

Play back in one thing, recording is another.

don

Move over to an ARM device from NXP. Most have audio interfaces (SSP compatible with TI IIRC).

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That would be 11,289,600 _Hz_, or 11.289600 MHz. 8051s were running comfortably at 11 MHz decades ago. :-) (the processor doesn't have to _generate_ the clock, just be fast enough to issue proper commands, read the data, etc., as far as I know.)

Have Fun! Rich

That's a standard I2S audio interface. Use some external logic chips and clock to dedcode this into parallel data and load into your micro at a much lower data rate using the LRCK signal as the data latch signal for example. Something like this perhaps:

Dave.

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Flash memory?

Bob

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8051.

I believe your analysis to be a bit befuddled. You cannot use the

8051 to directly generate the clocks, you must use other circuitry for that.=20 The total circuitry is a handful or so of gates and a common clock. An 8051 at 12 MHz is quite reasonable these days. You can use an 8051 to deal with the data rate which is serial at about 1.5 Mbit/s or use a couple of shift registers and parallelize it.

Use the same oscillator as you use for the uC. That's only 11.2MHz (not 11.2THz ;). The original 8051 was 12MHz.

Yes, and so is everyone else. ;-) The 256x "oversampling" clock is the delta-sigma modulator clock. It has nothing to do with the I2S interface or anything else. Do a search on "delta sigma converter" or "delta sigma modulator" for more information.

Anything but a PIC. ;-) BTW, Actel has an 8051 soft core (more than one, IIRC) for their FPGAs. Without looking at your application too closely, or knowing your budget, I'd think they would be a real possibility for you.

I think you can use a simple LPC2000 series microcontroller for this job. Its (timer) outputs are very fast (not all ARM controllers have this feature!). If you run the controller at 45.156MHz you can use a PWM output to divide the CPU clock by 4 and use the other timers to provide the rest of the synchronisation signals. The SPI interface can be used to capture the data. This way you'll have a single chip solution.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
                     "If it doesn\'t fit, use a bigger hammer!"
--------------------------------------------------------------