strained Si cmos

Sometimes search engines are faster than even newsgroups. ;-)

And please do your homework yourself, looking at all your recent post they sure all look like that ...

Sylvain

I do not understand what you mean. I have searched and googled and yahooed. Just the article did not tell much about the fabrication steps. Just the final cross sectional views So I dropped a posting and hope someone may be able to give one or two advice. I am not asking anyone to tell me to regoogle I hope you do not misunderstand me. And I found that engineered substrate comes with the top layer with strained Si layer, so I wonder if source and drain surface is strained si or will be deposit some other epi layers. I did do my google search. I just hope when people want to give advice, please give it with a open heart and rational thinking. It is not a homework too. It is something I wish to know through self reading. Thank you

Jason

By the way, before I sent out those enquiry , I have done many hours of online search and IEEE search. No need for me to convince anyone. Just whether someone wish to share opinion or not, he is to decide. Cheers

Jason

Hey, Jason! Where do you work, or where do you go to school?

Food for thought... would straining a highly doped region do much, if anything?

Conversely, how about a lightly doped invertible region (also known as the channel :)

To acquire your engineering stripes you need to do a little "what-iffing" on your own.

...Jim Thompson

I don't usually google, nor am I a yahoo, but search.com (searching on the amazing string; "strained silicon") pulls this one up right up on top (with a picture of the strained area and all):

I don't know *too* much about these things, but I do know how to use a search engine.

If you want to know about the fabrication steps, try a patent search. Such things are often the subjects of gazillions of patents. You might even try a search of

I find a lot of what you ask with a ten-second search.

Search some more! The pictures in the obvious links tell a story.

Trust me, what you're looking for *is* on-line, at least to the level you're asking. Those who really know their stuff here may not want to participate in the discussion, since much is proprietary. Web-searches are your friend!

Thank you Keith I found that page and was in pdf file few days back. I wonder if there is sites that shows one step by one step in constructing a strained cmos. For example, after halo implant, followed by heavy implant of source drain and then ... I will keep searching. Just that it has been few days search and did not find it. I just hope if someone knows it and can share with me. Thank you Keith.

Jason

Hi Jim

Thanks a lot for the food for thought. I do not know if straining would help or lightly doped invertible region would do better. That's why I have to find out about it. So far, many sites shows straining the Si will increase the mobility , therefore it is good choice when scaling a cmos down to deep submicron. As for a lightly doped invertible region, you mean the doped of boron to n channel and phosphorous to p channel , is it? If so, it is to smoothen the strong field as what I have read

I am going to school! :) Any other advice, please tell me Thank you all for writing back with positive and constructive discussion rather than critics that is not true!

Thank you all

Jason