0.6um CMOS IC process

Without knowing the specific answer, I don't see why you couldn't use Verilog / VHDL; after all, it's a synthesis tool and ultimately we (for any non-trivial stuff now, anyway) always run through some synthesis/compiler for PLDs of all shapes and sizes. One would assume it is only limited by manufacturer support.

The addition of analog functions makes the device more complex, but I don't see why it would make the Logic side synthesis any different (at least in broad terms).

Cheers

PeteS

Sure. It should be no problem. You can even simulate the analog function (at least in VHDL), if you have it all together. Of course analogs aren't likely to synthesize very well, but it should work fine on the digital parts.

Yes, it can be done. The process dimensions don't matter. The presence of analog _may_ complicate things, depending on how you approach your design and layout.

Most 0.6um processes are not heavily used in digital today, and don't include standard cell libraries and their associated synthesis and APR models. Make sure yours does before you start. Creating the requisite libraries and views is not a trivial task.

If your top level is a schematic, then you will be placing your top level synthesized digital as a black-box in your top-level layout. This may be the preferred approach, since the digital synthesis and APR can be completely separated from the analog design in this case.

If your top level is RTL (Verilog/VHDL), then you will be calling your analog blocks in your RTL code, and using an APR tool to place and route the top level. In general, this is more difficult to do, but once you've figured it out, it can make the final assembly go much faster.

In either case, I'm assuming that you have partitioned your analog and digital into separate blocks. If you haven't done that, or can't do that, your life will be much more difficult.

-- Mike --