Split Ground/Power planes for sensitive analog, vs glitchy digital

Fiber optics dosn't like sharp bends either.

Here's a TDR experiment.

The right angles are basically part of the background junk. The big bump is the via. The connector transitions are pretty bumpy too.

RA's are not something worth worrying about for most logic design. Maybe GigaComm logic with 35 ps edges. Certainly not CMOS.

Am 23.07.23 um 20:00 schrieb John Larkin:

My experiment is about the same:

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The SMA on the 4 layer board is much much better with the cut outs on layer 2 and 3. Maybe even very slightly inductive. The normal SMA for 2 layers was a capacitive disaster on 4 layers. The 2 SMA transitions are where 2 "ears" are on the trace.

The setup: <

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The result, TDR and through: <

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The microstrip is only 10 mils wide, correct is 11.5 mil for 50 Ohms.

Risetime is still OK, including port savers and semi rigid: <

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cheers, Gerhard

Both capacitance and inductance are affected, it isn't the same impedance-per-mm as the straight-line trace.

That is a result of internal strains, which REALLY change the impedance (even obliterate the anisotropy of the medium); gotta love the polarized light show. It's a very similar phenomenon, for all that it's photon waves instead of sea-of-electrons.

It makes some pretty pictures

Nice.

The serious microwave SMAs cost serious money, so we buy a very nice Shining Star edge-launch that has a fat center pin, so that gets a fat pad which is a lumped capacitance. The fix for that is to cut away some of the internal planes under the pin.

We simulated that with ATLC and it works very well.

"Rob1" is the final stackup.

That trick is also good with surface mount voltage references, which tend to be vulnerable to board stress.

Sensitive high-Z things also benefit from bootstrapping a bit of the ground plane.

Cheers

Phil Hobbs

The bend effect birefringence is quite small, and doesn't scatter light out of the fiber--it just screws up the polarization. Polarization compensators rely on bend birefringence to make the equivalent of three rotatable retarders--two quarter-wave and one half-wave. Thor Labs has a page on that:

. The light loss that you see when you bend the fiber in your fingers is actually a coupled-mode effect. When you bend the fiber into a circle, there is some radius at which the fiber mode will phase-match to a free-space wave in the cladding.

As you bend it tighter, that radius gets closer, and eventually the resulting coupling gets pretty strong.

Cheers

Phil Hobbs

I recently tried bootstrapping a bit of plane. It's a triggered phase-locked 50 MHz Colpitts oscillator and the horrible tempco of the FR4 capacitance (something like +9000 PPM/K) was wrecking the oscillator stability.

So I drove a guard patch, cut out of the ground plane under the oscillator, from the source of the SAV541 oscillator transistor. That made things worse.

It worked better to just cut a square-ish hole in the layer 2 ground plane and some power planes below, to reduce the overall capacitances.

I had a batch of custom 3.3 pF N4500 caps made too, to tweak the tempco to flat at the nominal operating temperature.

Bootstrapping a bit of plane makes sense for lower-frequency stuff. But the bootstrap driver needs to be super low noise too.

I do it with faster stuff than that, and it works great, eventually. ;)

Yup. Hundreds of picovolts to maybe a nanovolt in 1 Hz

It’s interesting that it didn’t help the tempco problem. I expect it may have been all the different phases of the 50 MHz that occur in an oscillator—the bootstrap waveform couldn’t be right for all of them.

TIAs are simpler that way.

Cheers

Phil Hobbs

That reminds me about some ancient EL families operating with something like Vcc= +1 V and Vee= -4 V so that logical levels were around Vbb=0 V.

With modern 3.3 V logic families, why not operate with a bipolar (say

+/- 1.65 V) supply and the analog side at say +/-5 V ? There would be no high currents in the 0 V plane, it would just carry the return current of signals between the analog and digital worlds.

It's been done - sort of.

LVDS used sub-ECL voltage swings from +1.0V up to 1.4V, and differential signalling

If you need a quiet back-plane that's one way to get it.

Last week an ambient superconductor was announced, could take a few years until it's in commercial production. (also contains lead, so they may need to find an alternative - also could be a mistake these guys have a reputation)

Here is an excellent guide for high-speed pc board layout:

For the vast majority of situations that is a bad idea. Often tought by acedemians who never really designed anything meaningful for industry, inclusing some at our university.

And like John said, of course that chip is the only one in the universe that needs access to two or more of the grounds :-)

The minute there is one more device like that the whole concept goes kablouie.

Think of two grounds as a dipole. Yeah, they are connected somewhere in the center but in RF terms that hardly means anything. Case in point: All the yagi antennas I ever built have a driven element that is one contiguous aluminum tube, no separation in the middle. Yet they radiate and receive as calculated. When you look at the gamma match concept I use to feed those it might become more clear where disaster can strike in a split ground system:

Another (noisy) IC, transistor stage or whatever somewhere off center connecting to one of the ground planes will make the whole contraption radiate. That can cause you to fail radiated and sometimes even conducted EMC. It also "receives", which may cause you to fail the susceptibility test which is nowadays part of the EMC test protocol.

In practice it usually doesn't. RF always tries to find another path around it, and finds it.

Exactly, and in practice you often can't. Outside stuff has to connect to your system. Mains power, protective earth, some sensors, maybe a keyboard, a touch screen that by its very nature can be touched by a conductive human finger, and so on.

I've been on the beat for many decades. In all that time I never saw a mixed-signal design with a split ground that worked reliably. Many times I was called in as a consultant to "make it work", upon which I removed all the ground splits. Often against vehement protests on the part of client engineers. My own designs never had split grounds and they always worked.

There are very few exceptions. In sensitive audio setups an occasional split can make sense but in my experience even there it's rare. Then there are safety rules. For example, in med-tech we must often maintain full defibrillator-proof isolation when used in cardiac situations, meaning it has to withstand 5kV. There the grounds aren't connected anywhere.

+1 John

"Acedemians" such as the chip designers? I guess their chips are not assembled onto boards for qualification.

That simply shows you don't understand the concept. Larkin says he uses the same idea. He simply rationalizes it as being different by saying he only cuts the area on "three sides" rather than talking about how they are connected.

You are ignoring that each chip which needs such a scheme can have its own analog ground area. Or, if the two chips can be placed side by side, they can share the connection between the common analog and digital ground planes. If neither is possible, then, no, this won't work. But then there are exactly zero techniques that work for every situation. In particular, the single, board wide ground area is not the best approach for some designs.

I don't know why you are trying to make antennas on the ground plane. There should be very, very little current flowing through the connection between the analog and digital ground areas, so very insignificant radiation.

As for susceptibility, how does the connection make the design more susceptible? Even an intact ground plane is susceptible to received radiation. It produces very little voltage because of the low resistance of the plane. Two connected planes can be connected with as low a resistance as desired, again, minimizing the induced voltage.

You aren't making sense. What RF from what source? What other paths?

I can't speak to designs I know nothing of. When you talk about "split planes", you make it sound like they are not connected. My concept is exactly like the scheme that Larkin uses. We only differ by how much connection is made between them. Larkin is simply afraid to extend the scheme to its fullest, practical use.

Ok, so then you agree with the concept. Thank you.

And yet, you manage to not have excessive noise, yes?

You seem to actually be saying all methods work. Ok, I won't disagree. I simply find the use of borders around noisy, or sensitive circuits, is a good way to isolate noise. You seem to agree, but, like Larkin, get all wigged out by talking about this being a reasonable idea, even though you eventually admit that it works.

I think enough has been said about this. There's nothing new in your post. You are agreeing with Larkin, who also agrees with me. You both simply have trouble admitting that you agree.

Pot of maybe a thousand board designs, I think I have done that twice, both times for boards with thermocouple inputs and high power drivers nearby. Just diverting some ground-plane currents around a sheltered niche.

Hilarious. I never join "analog ground" and "digital ground" under a chip, much less many chips. In fact, I never have two grounds.

Yes, exactly. Thank you for agreeing with me, finally.

Neither do I. When they are joined, they are only one ground, exactly as you have said you have done.

The cut in the ground plane here

keeps the thermocouple circuit from seeing microvolt potentials caused by voltage drops in the ground plane. But the amp circuits are still solidly grounded to the only ground.

Show us your board.

I don't have two grounds either. They are joined to form a single ground, just like you said you do.