Digital and Analog power decouplings

I don't know this series but how would they internally decouple? On a chip you can't create any caps to write home about. I guess they assume that the circuit designer maintains good bypassing.

No. I never split ground unless it must be done for safety reasons such as patient isolation. But this is my own humble opinion and almost guaranteed to set off a huge political debate within the next few milliseconds ;-)

#1 is the prevalent method. But it depends a bit on what consumes the most. So if you had analog stuff that uses 500mA and one uC that consumes 2mA then it would be #2, of course. Actually, I am doing that right now on a circuit that is 95% analog but needs a bus interface that consumes very little. On this one the analog rails must be super squeaky clean.

Unless they have very good fab process to build L & C on chip. Or they didn't think it was necessary. Or a design oversight. This could potentially push me over to the NXP.

Thanks.

L and C on a chip both cost oodles of real estate and for decoupling purposes they would be prohibitively expensive. Usually the only L and C you can find on chips would be on RF circuits in the GHz range and then you'd be talking about very few nanohenries and a few picofarads (but usually even femtofarads).

Well, I wouldn't expect stand-alone performance from an AD converter on a uC.

Most certainly not. Typically more of a compromise because people often want the lowest possible pin count and also because a larger package will cost more.

Always welcome.

Without power filtering, 10 bits might be meaningless.

But there are four power pins and four ground pins, they could have spare one for analog power. Avr has 2 digital power pins, 1 analog power pins and 3 ground pins.

With good bypass caps I've seen 12 bits work just fine.

Then they could indeed have split the power pins. Who knows, maybe the converter is in an area on the chip where it wouldn't have helped much. But that's hard to say without mask pictures.

L's cost oodles. C's are done on chip all the time. All of our whitespace was filled with decoupling C's. Of course caps are added to the packages too. When you're switching many amps...

The analog PLLs had separate AVdd pins too.

But you won't likely get enough pF to write home about. When a bunch of comparators are clanging around in an ADC there needs to be some serious capacitor close by to take the brunt.

Once when I redesigned a pre-amp on an RF chip I could have really, really used a fraction of a pF to get rid of a spike. So I went to the guy that was in charge of chips at that client and politely asked whether I can have that little corner lot over there. "Nope".

That is a smart thing to do.

Filter to the lower energy/smaller node, which normally means option 1.

When you say decouplings, do you mean Separate Analog/Power Pins ?

What's needed depends also on if you use the internal Vref, or external Vref, or do relative to Vcc.

A well specified device will give Power Supply Rejection ratios, for the analog sections. Some spec differing LSB errors, on the physical pin locations - expect the channels nearest GND pins to be better.

More important, is does the vendor specify a MAX, or only typicals? ( and at what Vcc's ) The better suppliers will spec their ADCs properly, the companies that 'add the tickbox', have lower standards.

-jg

Yes, need separate pins to have external filter.

No external Vref either.

I think they just forgot to hire an analog consultant before making the chip.

Lotsa nFs (don't remember exactly) in reverse biased junctions. The slew rate of the comparitors will be less so you would need quite a bit more C.

There was no white space on the chip. Any whitespace we had was automatically wired as decoupling. Warnings were generated if C got below some threshold.

Learned (and relearned) the hard way. Some parts called out a low- pass filter on AVdd. I could never figure out why each part was different (other than different engineers).

Most circuit design teams do that, too. And then when it hits the fan the phone rings...

In some applications it is possible to stop the clock of the digital section while taking analog readings. If your application is such that you can do this it pretty much eliminates digital noise in the analog readings.

I have seen this done. It is sometimes less tricky than it sounds. The ADC busy/done signal can tell you when to start it up again. Many micro controllers don't object to having the clock stopped for a short time.

Another thing that helps is to make the phase of the clock on the ADC such that it decides on bits just before the active edge of the clock to the digital stuff. Digital noise tends to be a spike right at the time when the lines move that then tails away.