Spicing pcb traces

as long as the bank voltage is correct for the io standard Xilinx can do diff_term you just need to enable it. Termination still works if the voltage is different, e.g. using LVDS inputs in a 3.3V powered bank but it might not be 100R

Can't you add your on termination resistor? You can hone it to match trace impedances.

Unfortunately, the diff pair is into a 1.8 volt bank. Don't blame me, I'm not the FPGA designer. I think there were other reasons for that choice.

The comparator is full-swing 3.3V PECL, so I added the 100 ohm pack to make 50 ohm sources and bet into the receiver common-mode range. But we gave up swing so probably compromised jitter.

It might be possible to solder a tiny resistor onto the micro-vias under the FPGA. Last resort!

Under-termination (too high a resistor) would add some overshoot, which would be good to sharpen up the rise time and equalize trace losses.

The system is theoretically source terminated, but the simulated waveforms at the FPGA are much nicer with termination.

Some of my jitter is likely caused by going through the FPGA, which is doing some other stuff and may have crosstalk and ground bounce and such. I didn't have room to do all the trigger logic with discrete logic.

that's on the guy that drew the schematic ;)

but just try, I've only seen some Xilinx guys say that running LVDS inputs* will work at any voltage that termination just isn't characterized

The pcb design is frozen?

Well, we've built a few rev A boards and we're finishing up the uP code and the FPGAs and the display/web pages and such. There are a couple of small kluges, but we can probably sell rev A. But I definitely want to do a B soon, and track down and kill that jitter somehow. I'm seeing around 7 ps RMS through the whole box, and I wanted 1 or maybe 2. Well, 5 maybe.

This pulser has a gorgeous output stage, and the SOT89 fast PNPs and phemts are all discontinued. Bummer. So I'll have to redesign that part some day anyhow.

I'll send you one when it's working right.

Your tools don't have a PCB signal quality simulation?

Wonder if the switch has an IBIS model.

Tim

-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Design Website:

DNLS350Y and DPLS350Y. SOT89, active, instock. Use to beef up SiC gate drive and dissipate heat in place of the gate-driver IC, for high frequency pulse rate. Let the driver provide 1A (Rbe=0R68), and these fast SOT89 BJTs provide 4A or more.

OK, thanks!

Alas, too slow for my circuit, and the phemts that they drive are EOL too.

I am using BFQ149 5GHZ SOT89 PNPs to drive the departed Avago/Broadcom phemts. We bought 12K of the PNPs so there's no rush to redesign, but I am developing a new GaN output stage anyhow. That's sort of my hobby, pulse generator output stages. (This is not the SiC high voltage thing; that's another product.)

Sot89 is a great package but looks to be increasingly rare.

You'll like it. It's beautiful.

No, I don't have tools for that.

A real IBIS-type sim - comparator, traces, polarity switch, traces, FPGA - would be a big deal. The Spice model was an easy Sunday afternoon thing. My FPGA folks preferred that I use the crossover switch, rather than doing a programmable inversion inside the FPGA. After lunch I'll ask them why.

The DPDT trigger polarity crossover is a TI USB switch. Some of these digital bus switches are really fast, cheap analog multiplexers that work great for routing logic with basically zero prop delay.

??? Altium can do it in a couple hours. :-|

Tim

??? We don't run Altium!

I don't see an IBIS model for ADCMP561 or TS3USB30. Haven't looked at Xilinx.

tirsdag den 2. april 2019 kl. 01.20.05 UTC+2 skrev John Larkin:

Demo I saw, FPGA doing video camera stuff, took seconds. As for SPICE calcs, depends entire on setting choices.

Since it's at the end of the line, it's the model that I need the least.