soft-start blunder (2023 Update)

Do the capacitors in series with the primary help prevent that?

piglet

They are there to keep DC current out of the transformer primary. If the half-bridge duty cycles were slightly different, we could have some net DC voltage, and the effective loop resistance is milliohms.

For some reason, this simulation shows a -45V Vgs after the positive

7.5V or so Vgs and then ramps back to zero V. Might want a zener Vgs limit.

Did you think about adding a simple-ish current limiting stop to the PWM with small value FET source resistor feedback ? Peak current mode.

boB

PWMing a capacitive energy transfer is the actual 'hack', but FPGA deconfiguration is a symptoom that won't go away, just because it was avoided, this time.

Need to harden your housekeeping supply and power rail sequencing strategy.

RL

Good point. I tested a fet and the gate started conducting around 50 volts and failed after a few seconds. Lots of fets have gate zeners but this one doesn't.

That might be awkward, given the board layout. This board actually has two of those forward converters, and I can soft-start both with the single ramper thing in the common 48v supply.

Doesn't sound like a bad idea, really. Have you played with frequency, or just the duty cycle? If a very short duty cycle and very low initial frequency still hose the FPGA, the problem is going to be unwanted coupling somewhere, probably between different power buses.

-- john, KE5FX

I'm guessing that the first bridge turn-on pushes hundreds of amps into the ground plane and makes potentials everywhere. If we make a square wave into the bridge drive and ramp up the +48 from a bench supply, it's all nice.

But the parts you're using have a frequency response that's not infinite. You can turn them on as slowly as you want by scheduling both the duty cycle and frequency of the pulses.

Pulse pairs spaced 5 ns apart aren't going to make it draw hundreds of amps, right? They will never make it through the gate drivers. How about

100 ns apart? Maybe it draws 10 mA now. 1000 ns on, then off? Maybe now it's 500 mA. Etc.

-- john, KE5FX

On a sunny day (Wed, 14 Dec 2022 09:01:50 -0800) it happened John Larkin snipped-for-privacy@highlandSNIPMEtechnology.com wrote in snipped-for-privacy@4ax.com:

Cannot read ASCII but small series inductor shorted after power-up before secondary rectifier capacitor? Only takes one power MOSFET?

Here's an improved version.

The FPGA will start up the 250 KHz square wave into the h-bridge drivers, and then enable the 48 volt linear ramp. That should start up nice and smooth.

My weekend assignment is to lay out the kluge board.

Hmm, it looks to be a forwards converter topology, so volts in is basically proportional to volts out, your only lattitude to regulate the output seems to be messing with the frequency, or doing "burp mode"

- which is still messing with the frequency just with less distortion to the spectrum.

You could get a half-voltage mode by only running one half of the bridge.

Putting an inductor between the bridge rectifier and the capacitor could help PWM response.

It is possible to do soft start on a bridge configuration like this. Like you mention, you need to be able to generate very close matching duty cycles to start with ns ON cycles.

Normally you would have an output inductor, since otherwise only leakage inductances limits the currents

I seems that the gate drivers won't pass very narrow pulses, and we'd have to tease the fet gate thresholds in some analog manner. We tried FPGA things that didn't work.

The +48 ramper works and is an easy analog fix. 8 little parts, 10 if I include an LED.

Just a little warm. At max current load, it's mostly copper/skin loss, but not much.

The giant peak currents on the first short pulse are't magnetizing current, it's from the bridge rectifiers and caps on the secondary. This Coilcraft planar transformer is in fact too good.

torsdag den 15. december 2022 kl. 16.35.42 UTC+1 skrev John Larkin:

so don't use narrow pulses, run both half bridges at 50/50 duty cycle and delay one of them 0-180 degrees

That is morally equivalent to starting with narrow pulses.

The way the drivers are wired, we can't do that anyhow.

Yes, that was actually what I suggested also :-)

On a sunny day (Wed, 14 Dec 2022 22:45:39 -0800) it happened John Larkin snipped-for-privacy@highlandSNIPMEtechnology.com wrote in snipped-for-privacy@4ax.com:

This was what I thought of:

the output voltage increases the inductor is shorted by the power MOSFET. Sorry for bad drawing here in zero graffiti Doing things low power is easier of course.

Yesterday I fixed a satellite receiver by replacing a STI8035 (LNB power controller). Now that was a fight getting the bad (shorted one) of the board and then also replacing some caps, the old caps were even smaller than the smallest SMDs I have, replaced those by mine connected with wires.. The new sat box I got recently (while waiting for the parts) is even HALF the size of the old one,

had a look inside, same circuit and software!! how long will we be able to repair stuff without a microscope??

ebay selller send me some chips from France, really quick. China specified end February or something.

The old China made box did leave out the protection diodes suggested in the STI8035 data sheet, so bang... There was space and pads for those on the PCB... Then again what you can get for 25$ is amazing.... I pay more for the box and connectors alone, But of course problem plenty: every Chinese thing has the same remotes these days..

switch off your sat receiver then your terrestrial TV tuner is off too! The new smaller one has the same remote but seems to use different codes so that fixes that problem.

I don't think the inductor would be a practical size.

Here's my soft-start board.

It bolts onto the power supply board where the fuseholder used to be. It replicates the fuse and adds the soft start, under FPGA control.

I like to lay out a small board now and then.