Hi,
I've been trying some analog IC design but I'm running into difficulty with things conceptually ("seeing" what is going on in the circuit) and practically (getting something I've made to work, in simulation) - ie. moving beyond what I was taught at university.
Specifically for the latter, I keep running into problems with getting FETs to run in saturation. For example, an NMOS cascoded current mirror: I've got the two cascoded input transistors on the left with drain and gate connected, so no matter what, these will always be in saturation. Then, connecting the gates of these biasing transistors to the gates of two cascoded output transistors, with the same Vgs, the output transistors should operate with the same drain current. But I've got an active PMOS load above the current mirror and it is dropping about 2.4V (with 2.5V supply rails), leaving only a few mV across the drain-source of the cascoded output transistors, so that they operate in their linear region instead of in saturation. The input transistors have an almost identical load as the output, but as they have their gate and drain tied together, they do stay in saturation.
So I guess my question is: how do I go about stopping the PMOS load dropping all my voltage? The PMOS and NMOS transistors have W/L ratios such that the PMOS is 1.5 times the NMOS, but changing these ratios doesn't seem to have a significant effect on the output NMOS Vds.
Thanks for any enlightenment!
Bill