Good morning. I have a couple of basic MOSFET questions that I would like to clarify. I have studied a lot of articles, asked a few people about this doubt but could not find a satisfactory explanation. I am hoping somebody will take the trouble of clarifying my doubt.
MOSFETs, as I understand, are voltage-controlled devices. Doesn't that mean that they need a charge (voltage) applied to the gate to make the device conducting? If this is the case, in some circuits I have found in the process of learning analog VLSI, what is the meaning of a "gate of a nmos/pmos transistor being driven by the output of a current mirror?" I have read that the output current of the current mirror is used to bias a next stage. What exactly does this mean?
Secondly, if the MOSFETs are voltage-controlled devices, why do we most of the time deal with currents when talking about VLSI systems?
Hope, I am clear with my questions. Thanks in advance.
If you force charge onto the gate of a MOSFET, you change the gate-source voltage. MOSFETs are voltage-controlled devices because the drain current depends on the gate-source voltage. It doesn't matter where the charge came from.
The gate is basically a capacitor which obeys the rule Q=CV
So, let me restate what I understood. The current mirror's output current is used to charge the gate of the transistor. So, depending on the magnitude of the current, the gate voltage increaser faster or slower (sorry about my layman language, I just want to be very very clear).
If I understood this correctly, then: 1) If a current mirror is charging the gate of a transistor, or in other words, changing its Vgs, the maximum Vgs value is determined by the saturation voltage for the mirror. 2) We are controlling the rate at which gate is charged in a circuit.
Have I understood this correctly? Thanks in advance.
Charge and voltage are not the same thing. The gates of mos transistors are nonlinear capacitors. To change the voltage of any capacitors involves movement of charge, The rate of movement of charge with respect to time is called current.
A current mirror provides a controlled current that passes charge into or out of the gate. When the gate voltage reaches the saturation voltage for the mirror, the current ceases, and the maximum or minimum voltage that the mirror can drive into (called its compliance) has been reached.
It means that the gate voltage is changed at a controlled rate by the controlled current from a current mirror.
(snip)
The speed of mos logic is limited by the current one stage can deliver to change the gate voltage on the succeeding stage. Voltage may turn the mos transistor on, but current determines how fast a mos transistor can go from off to on or vice versa.
I have one question, how do we know how much current we have to generate from a current mirror to bias a transistor. I know this is a vague question, what I mean is, the gate capacitance determines the rate at which the gate will be charged, right? So, are the gate capacitances values standard for different transistors? Where are they available from?
For instance, in an example, if the author says that a current mirror outputs constantly 200nA to the input of the gate of some transistor M1, he means that the gate voltage is being maintained constant (unchaged) with this small current. The exact values, I assume, can be obtained from the specific data sheets are manuals.
That is the principle. For linear capacitors, the math is I=C*(dv/dt), where I is amperes of current, C is capacitance in farads and dv/dt is the the rate of voltage change in volts per second. Unchanging gate voltage requires only leakage current to be maintained, and that is a very small current for mos gates.
Yes.
You have restated what I said, so if you are wrong, we are both wrong.
The logic speed of a mos system is based on both the current the drains can deliver to the next stage gate, and the capacitance of that gate.
The gate capacitance is as low as the maker knows how to make it, and the drain conductance is as high as the maker can make it. We are stuck with what is available based on physics and the state of technology at the time the device was made. If they make the transistor larger, to raise the drain current, the gate capacitance goes up. If they make the transistor smaller to shrink the gate capacitance, the drain current goes down. So the details of gate insulation thickness, channel doping profiles, and lots of other details are the difference between the best combination and average (or below average) performance. This is what keeps chip designers working overtime and forever.
If the circuit is logic, the current source (not usually a mirror, but just a common source amplifier) never holds the gate biased half way on, but is always either saturated full on, full off, or is transitioning between those saturation values as fast as it can charge the gate capacitance.
For analog circuits (like opamps) there are usually two current mirrors battling it out, one trying to charge the gate up and one trying to dump the charge out of it, and in the steady state case, one current mirror is pouring current into the other one, and the gate charge is sitting unchanging somewhere at a middle voltage. Then the two mirrors unbalance from a change in the signal and the gate swings to another voltage, till the feedback rebalances the mirrors to a standstill.
For instance, in this simple opamp:
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Q3 and Q5 are a pull up current mirror (that supplies a constant pull up current) and Q11 is a variable pull down current source dependent on the balance of the two input voltages. The output of the opamp (the drains of Q8 and Q12) depends on what voltage there is on the gates of Q8 and Q12 when the pull up and pull down current sources on their gates become equal and stop supplying either pull up or pull down current to charge them. If those two currents are not equal, the remainder will go into changing the gate voltage and the output voltage will be in slew.
Overall, I'd say you didn't understand it, and it wasn't explained real well to you, but maybe I just don't understand what you and others have said.
First off, MOSFETs are generally considered to be voltage controlled current sources, at least when operated in the saturation regime (Vds > Vgs - Vt). BJTs on the other hand are current controlled current sources. Each of these transistors have respective advantages.
In analog circuitry you often deal with both voltage and current, and since MOSFETs are voltage controlled current sources its important to consider all aspects. MOSFETs are complicated devices, entire books have been written simply discussing aspects of how MOSFETs work. To try to boil them down into one or two sentences will surely leave you with an incorrect understanding. Even the most cursory treatment of them in an engineering text book would be at least several pages long.
The purpose of a current mirror is to duplicate (or mirror) a current with some sort of multiplicative factor (M/N). If you are following good layout practices, M and N should both be integers. Let's say we have a simple N-channel mirror, where M and N are both 1. So we have two identical transistors (M1 and M2). M1 and M2's gates are both tied together and tied to the drain of M1. M1 and M2's source is tied to ground. A current, I1 is pushed into the drain of M1. M1 is said to be "diode connected" because its drain and gate are shorted together.
Now, let's ignore M2 for the moment. If we take M1 to be an ideal transistor, no current will enter the gate of M1, so all of I1 must enter the drain. The gate however is capacitive, as such its voltage can be increased by pumping current in, or decreased by pumping current out. The gate has access to a current source (I1) to increase or decrease the gate voltage so as to allow all the current to flow through the drain. It should be obvious that as its adjusting the gate voltage the current through the drain will not perfectly match I1, but it should get closer and closer over time. Eventually the gate voltage will be forced to settle to whatever voltage will produce drain current equal to I1. Assume for the moment that M1 is biased into saturation:
Id = K * (W/L) * (Vgs - Vth)^2 * (1 + Lambda*Vds)
Lambda is the channel length modulation and is often quite small. It can intentionally be made small by increasing L (gate length). K and Vth are constants that are fixed by the processing. W and L are the gate width and length respectively and are chosen by the designer.
Now, let's add M2 back into the circuit. M2's gate is shorted to M1's. M2's source is shorted to M1's. If we look at the Id equation, assuming identical W/L, the current through the drain of M2 should closely match that of M1. In real designs the designer may use different W's for M1 and M2 in order to achieve the multiplicative effect I previously mentioned.
I don't think all that much thought is given to the amount of current required to charge the gate of the MOSFET, unless speed is a concern in which case there are much more advanced and accurate topologies that can be used. Typically current mirrors are used for providing a static bias current to multiple points within a circuit based on a single reference. In this case, the reference rarely moves, and speed simply isn't a concern, and hence no one thinks about the charge rate. There are other instances when an AC signal is being mirrored in which case it may be more of a concern however.
So the current mirror's *INPUT* current is used to charge the gates of the mirror transistors. The output current could be used for a variety of things depending on why a mirror was even employed to begin with. Regarding your assertion about the maximum voltage... The only criteria on a current mirror and voltage is that the transistors (both of them) must remain in saturation (i.e. Vds > Vgs - Vth). If the transistors slip into triode region, then the transistors cease to act as very good current sources, and start acting more like resistors, as such the mirror becomes far less effective if the loads on the mirror branches differ substantially.
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