Hello
I describre my problem below and hope you'll help me.
I am working on low power LDO. First i did simulation with simple one stage OTA (nmos input) plus power PMOS and feedback. The lowest Vdd is 1.3 so PMOS has to be quite big to drive 100mA. OTA has big output resistance, when working with low bias current and it causes, the parasitic pole of output resistance and pmos input capacity is in low frequecies. It deteriorates GBW, load regulation and so on.
I want to use voltage buffer to send this pole to higher freq. I used simple pmos or nmos source follower but it's not efficient to fully turn on or turn off this transistor.
So i used the same OTA in the buffer configuration. Its characteristic is ok, the slope 1. It repeats input voltage to output. But the problem is with low Vdd. It's 1.3V and i need about 0.3V at the output to drive
100mA from pass device. This inut voltage causes, the inputs transistor (nmos) are cuttoff so the output resistance is big. With low load conditions everything is all right. Transistors work in saturation and output resistance is low.Could you recommend any tuning or circuit which will work fine?
regards
jutek