Do you try to do it on your own? How do you know all the balls are soldered correctly? X-ray checking is not a problem if the production scale is high, but what do you do in the case of prototypes or batches of
I do too, depending of course on why I'm doing the proto. Sometimes you have to do real SMD prototyping, like that 120-ps single-diode TDR that ChesterW and I did early this year--0402s and 0603s in mid air. Good for the patience, that. ;)
Far mor reliable even though there is no thermal stress relieve mechanism? Electrically far superior than anything else, but mechanically it is a disaster waiting to happen. IMVHO.
But in real life, BGAs are amazingly reliable, far better than leaded parts, both at initial production and in the field. Our BGA per-pin initial failure rate is ballpark 1 PPM, and I don't think we've had any field failures. I didn't anticipate that myself.
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John Larkin Highland Technology, Inc
picosecond timing precision measurement
Good to know, maybe I should give them a chance. So now a practical question: IIRC you are using ZynQ in your devices. Do you design your own PCBs for them or use the ready-made modules like the Zeds? If the former, then what number of layers do you consider to be the bare minimum to route all that insane CL* package signals reliably? Can you do it on 4 layers?
we make our own and use 10 layers, I doubt 4 layers are realistic, before you done anything you need 3+ different supplies, and a bunch length matched wires to the DDR RAM
for low volume I think it is had to beat a module
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a module with 1GB RAM, flash, ethernet, etc. for $99, the Zynq alone at digikey cost +$60
Holy Cow, assume there was no question... Thanks, all!
The problem with modules is that they contain a lot of things you don't need, but do not contain the ones you really do need, so the resulting system is a Frankenstein wired of random boards. But if you say 10 layers, then well, what can I do..?
Those are nicely stuffed, but like the Zeds, they are more dev boards than embeddable modules. Trenz also has a lot of interesting modules, but for some reason he doggedly pursues only the 4x5 form factor and I simply have no room for a horizontally-mounted module. So for me this seems to be the only game in town:
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but I am concerned about the long-term SO-DIMM contacts reliability.
Depends very much on the size, and whether you use underfill or not. With good thermal management and good underfill, you can make flip-chips of 20-22 mm square without ripping the corner leads off the base level metal (BLM). Organic mezzanine packaging makes this easier.
We did a single DDR ram on our ZYNQ board. One DRAM doesn't need the awful address and data line terminators and associated term supply that two or more chips would need; I think we only terminated the single clock pair.
I could share those schematic and layout snippets if anyone is interested.
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John Larkin Highland Technology, Inc
picosecond timing precision measurement
Underfilling and similar thermal stress management techniques are acceptable if your name is Samsung or another IBM. Otherwise how do you know you're doing it properly? I'm afraid that a similar phenomenon to the fabless semiconductor companies is about to happen: smaller shops will soon be unable to manufacture their own designs and centralized assemblers will emerge, similar to what TSMC is in the silicon world.
Absolutely, except in a 10-pF single-diode sampler with an 0402 Schottky di ode.
You'd be wrong about that. The sampler is the little bit centering on the s ilver semi-rigid coax. All the schmutz around the outside is support stuff-
-the Tx and sampling pulse generators, delay scanner, and so on.
The actual sampler is nice and clean, has an RMS jitter less than 10 ps end
-to-end (0.1 inch gauge length on an air line), and costs $2.
Plus you're just crabby about not getting to Truckee for the weekend. ;)
That is no justification for such a hideous breadboard. If I was that ugly, I wouldn't work at all.
Here's my old 2-diode sampler. 70 ps, 5 GHz, hand etched.
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I recently did a PCB of a TDR based on a d-flop 1-bit sampler [1], but I haven't had time to fire it up. I'd expect maybe 50 ps, after a bit of digital processing.
I think Joerg did a single-diode TDR recently, too.
With a bit of deconvolution math, all you need to do is make a really ugly sampler and, as long as part of the step response is fast, you can beautify it in the PC.
Oh no, I much prefer staying at home in the smoke, repairing the rot on the deck, standing on a ladder ratcheting lag screws over my head.
[1] sort of like the dflop phase detector.
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John Larkin Highland Technology, Inc
lunatic fringe electronics
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