Short track and impedance matching

Why the emphasis on getting 50R transmission line impedance? You can't get all that far away from it. but a wider track with a somewhat lower impedance would give you lower losses,

A potential problem with an FR4 resin bonded glass fibre board is that the periodicity in the woven glass fibre mesh inserts small regular impedance variations along the track. I've never known it to be a problem, but my narrowest pulse was only 500psec wide, which isn't all that fast.

Rogers boards tend to be a lot more uniform, but weaker.

Use FR4. Have a suitable decoupling capacitor right next to the FET switch. Augment the decoupling with very short connections to a relatively large power plane - ideally several interleaved ground and power planes to make a distributed interleaved capacitor. Use multiple vias to get a low inductance connection to the power plane(s) and lots of vias to stitch all the ground areas together. Place the vias slightly randomly to avoid creating regular structures. Most of the power supply inductance will then be right next to the switch, so use the widest tracks you can along with the thinnest layer spacing for highest capacitance.

John

That is my point exactly. With a small distance, no need to do simulation in ADS, and reflections will be kept low.

Yes, and there is also a small effect on how uniform the copper is. When it is rolled on, there are mountains and valleys, so the HF signal will travel longer for small skindepts. The info I have from the manufacturer is that the valleys are max 10% of the copper thickness. So wont add much resistance either.

Yes, that's how I plan to do it. A big ground plane in several layers, components tight, and placed in a circle to reduce path length even more. And then a small 2mm trace on the path. As you say multiple vias, since one via adds 1nH in itself. If possible no vias in the signal path since then I would need image vias also.

Where do you get a gate driver that can turn on a GaN fet in 500 ps? I need that! A little inductance in series with the gate could help some. The gate resistor will slow things down.

Actually, I need to drive a capacitive load, an optical thing, to maybe 25 volts in 1 ns. Up and down! At 100 MHz!

I can't disclose the application. Even I'm not allowed to know the application. Something related to war, maybe.

I like to use the small EPC parts, the tiny 4-ball things, for stuff like this, but I;ve never seen, in real life, the sorts of speeds I see in Spice.

The PCB dielectric won't matter. The part and trace parasitics sure will.

Envision copper pours, lots of paralleled caps, and very short traces.

Inductive peaking of the load could help.

Your "50 ohm" guy is driven by convention and not thinking. That happens a lot.

You can ignore dielectric losses and trace resistance/skin effects in what must be a tiny structure. We do much faster stuff on FR4.

This is a modulator, one of 48, for a largish laser. It's all FR4.

That's probably because you don't bother to put in the small lead inductances that matter at those sorts of speeds.

The PCB dielectric can matter. The parasitics can be modelled in Spice, but it's tedious work.

A 50R transmission line can be terminated with a 50R resistor. If the 50pF is distributed along the transmission line the rules are different.

It's relatively easy to get a transmission line to have an impedance of 50R, and relatively easy to work on them. Going to the trouble of setting up something different does make life more complicated. Thinking about that isn't "not thinking".

LMG1020

It's going to have a lot of charge losses, depending on the parasitics of course ;-)

Yeah, my opinion also. Just wanted to hear other input before getting into the nitty gritty with him. He's a good guy, just a little too focused on impedance matching

I agree. I've only ever seen impedance matching in signal propagation, not power distribution. In power distribution, it's more a matter of reducing losses and resonances. However, one of the classic mistakes in PDS is assuming you need to treat each power cap as a discrete device, connected to the chip with wires. So people focus on "loop impedance" and such. In reality, the power planes form a transmission line, supplying current to/from the capacitor with distance from the chip being a very small factor. In fact, power planes form resonant structures based on the distances to the edges where reflections occur.

But yeah, there's no real math to show treating your 2 x 10 mm connection needs to be analyzed as a transmission line. The point of a transmission line would be to match impedances. What is the impedance of your capacitor? Wouldn't you want to match that to the transmission line, when doing such an analysis? I can't imagine why 50 ohms would be the magic number.

This is a case where the loop inductance would be significant, and that means the path from the decoupling cap on the FET drain to the load capacitor. After all, that's where the power is going to come from... that, and the power planes.

Why 10 mm? Is that as close as you can get them?

1. When the delay time is greater than the rise time then impedance mismatches between the line and either end will create reflections.

1. When matched to the line at one end only, it is best to match the source. ( e.g. CMOS 33 ohms 1ns drivers to 200 ohm cable, add the difference to source to eliminate overshoot. )

2. When delay is less than rise time, the delay will further attenuate signals with 1/4 wave cyclic ripple.

If you seriously want to match impedances to maximize rise time you would have a very low impedance (=driver or load) 3 ohm transmission line which would radiate more drive current and cause more crosstalk issues.

A 50 Ohm line is pretty easy to choose with aq trace width/Gap to ground plane of 2/1 for FR4 and easier with multi layer thin laminate Gap.

Yes, and placement of the capacitor does not need to be right at the IC. Feranec has some great videos on the subject:

Yes, that is the total path, including some components in series to limit peak currents to protect the FET. I wrote to EPC, and even though the peak currents are for sub ns, they recommended to not have the peak current more than 2-3 times the rated current of the FET

Nice part. Do you even need a GaN fet?

Shame it's a single 5-volt driver, not one of those bootstrap half-bridge drivers.

One might drive a GaN fet half bridge with two of those. One would be grounded, but the other would have to float on the source of the upper fet. Getting power up there would be no big deal, but the logic drive would be interesting.

In our design we use a digital opto to do the levelshift. Downside is that the switch node goes to several components so has some capacitance.

One option is to use the LMG1210 which is a high side driver, has a little slower switching speed however.

GaNs are several times faster than standard FETs

Nice but slow.

I did my own output stage for our digital delay generators, a half-bridge with GaN fets. I did it as a throwaway mouse-bite PCB subassembly because the tiny EPC parts are so fragile and hard to rework.

I meant, can you just use the TI driver? Maybe you need more voltage into your cap than 5 volts.

Maybe you only need to use the lower, the pull-down, drain.

Maybe it's good for more than 5 volts!

I see what you mean. I need up to 50V into the capacitor.