I have several chips that use serial communication(There SDI/SDO's are all cascaded). To reduce the overall clock length feeding these chips(which would stretch 10's of inches) I fan the clock(split the clock line and spread out to each chip).
The maximum trace length from the uC to the furthest chip is about
10inches and there are a few stubs in between(very short stubs) .I noticed that my clock lines were ringing pretty severly on both the positive and negative halfs. Everything seems to function properly but I'm wondering why they are ringing. The clock run about 1Mhz and the rise time is as fast as the uC handles it. On the scope I would say it's about 100ns or so.
I'm not sure if the scope is causing the ringing or what. I have another clock that has about a quarter of the trace length that looks to have identical ringing.
I did not terminate the lines since the calculations didn't warrant it. It was the whole reason I fanned out the clock to avoid a real long clock line which would have required termination(not a big deal but it would have also introduced skew). Maybe this wasn't such a good idea?
What I have essentially is severalines, two of which look like
+------*---+-------*------* | | +------*---+-------*------*Where * are stubs(IC's) and the | are bridges. The clock enters from the left. I bridged the clock lines in the middle thinking it would help equalize the clock but maybe the difference in the two paths are creating some weird reflections.
The peak of the initial transient of the ring is close to 1/3 of the clock so it is rather significant.
When I get a chance I'll try to terminate the line and see if that helps but was interested in some of your thoughts while I wait.