Re: TCLE

I did something similar with an LT1016 a long time ago. But it may not be fast enough or cheap enough.

and if you use the T version the two will combine to a ~50-60R termination

Thanks, but I'm driving single-ended from an Efinix FPGA so I don't want to end terminate. And I have the hi-Z receivers in stock.

LVDS would have been interesting, but the host PCB is done. This stuff will go on a little baby board, with a 70 ohm ribbon cable.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

single ended source into an input terminated to VCC/2 would basically be similar to Single-Ended HSTL, commonly used for memory

Sure, but source termnated, hi-Z load, would work too. Arguably better, since we'd have twice the swing and twice the slew rate at the receiver. Less power too.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

Nice! DAC R values trial and error?

Since the source termination has to include the output impedance of the driver which is going to vary with current and output voltage, it's a poorer quality termination.

There's also the catch that if the receiver end rings outside the rails, you can inject current into the receiver integrated circuit substrate, which has been known to have unfortunate side-effects.

No, they were planned to be R-2R and to get the filter impedance right, but I did tweak R44 to get monotonicity at the MSB transition. That corrects for the roughly 10 ohms source resistance inside the FPGA.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

And there's only one receiver, right? Otherwise you'll be applying half signal level to some of them until the reflection works it way back, resulting in possible metastability. Source terminated works best with very fast signal edge rates. Does that Tiny Logic drive those low impedances, somewhere in the 100- 300 ohm range, to full VinH,min and VinL,max, or is the receiver not a logic gate?

That so-called elegant solution with the '245 reminds me of the days of MSI logic CPUs with all sorts of multi-phase clock references all over the place, anything of any complexity consumed kilowatts, and the cooling exhaust air was coming out hot enough to burn your hands. The 5V was routed on true bus bars about 1/2 inch thick.

All they did with the 74245 was tap off the conventional TTL phase splitter used to drive a single totempole output, and use it to drive two totempoles, true and complementary. The phase splitter outputs totempole drives were mirror images and in that way achieved theoretical zero skew. Looks like they were after eliminating transmission line common mode reflection with that skew performance, so the market went away with the necessity to drive clock signals tens of feet in distance.

I can try. Insight is in the mind of the beholder, and some ideas are hard to get across, and certainly there were some junior engineers who took a while to get the message.

I got much more comfortable with transformer design after I'd been exposed to the Siemens soft-ferrites application notes, which spelled out the transformer equation. The Mullard Ferrocube application notes had been much less helpful. Other people don't report having the same kind of reaction. Some people do seem to find some ideas hard to get their heads around. There is an Irish expression - if I wanted to get there, I wouldn't have started from here - which may be relevant.

Edward Rawde does seem to be talking about the the very low distortion sine wave oscillator thread. He didn't have much insight into what was going on there, and has been remarkably happy about his own half-baked contributions ever since.

The earliest description I can find for that oscillator (which is the same one JM used) in filter form rather than oscillator form which requires one more resistor is

Very nice! that step correction!

That Rigol DS4034 is a nice scope too, bit expensive..

The original PDP11/20 (I had one of the first ones) was two giant boards full of TTL. It was horrible.

My setup will be

T20 FPGA output pin pcb trace ribbon cable pcb trace two TinyLogic xor gates close together, as my phase splitter

all powered by 3.3 volts. Total length maybe 4 inches.

We'll select an FPGA pin drive strength to about source-terminate 75 ohms. The actual choices (there are four) are a bit under and over 75 ohms, so we'll go under, which will create a bit of overshoot at the xor gates. That will crisp things up.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

Isn't that basically a state-variable filter topology? I am sure goes back earlier than 1978 - I recall seeing it in the 1972 Natsemi LM3900 app note and even then it was not a new topology, I think it was well known in 1960s if not earlier?

piglet

Looks good enough to us. It's just logic. One of my guys will scope it and I can post pics.

Some people just don't like source termination.

The old CD4000A cmos logic would latch up and fry if a signal gently touched the ESD diodes. Modern cmos parts are typically specified to tolerate 50 mA but I've never seen one latch up.

I have seen some mixed-signal parts latch up, like DACs. Maybe a semi process that does good analog is not optimized for logic. Or maybe the superstars at Analog Devices are the analog guys and not much care is given to the digital bits of a chip.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

Am 05.05.26 um 20:15 schrieb someone:

This circuit: 2*74LVC04 + 2*100R ser running at 5V (well inside Vabs max)

delivers that into a scope, switched to Zin = 50 Ohm:

click to > once or twice.

Sorry for the colors, they look better on the screen than in the screen dump. I'd say: Good enough for 3V3 74LVC input with 50R parallel termination.

Without the series resistors, it's probably OK for 5V CMOS. Just keep the micro strip at 50 Ohm then.

Gerhard

Depends on what you mean.

It’ll overvolt the receiver for one round trip time, because the outgoing amplitude will be more than half the logic swing, and so the initial edge at the receiver will be taller, but it won’t improve the rise time.

You’ll also get pulse top artifacts for a few round trip times. That’s probably not a big worry unless your rep rate is too high. Of course if they get too large, the input diodes will help. (One can diode-terminate ECL.)

Cheers

Phil Hobbs

Yes

I was curious about its origins. The term Bi-Quad also seems to be used. See fig 40