Re: TCLE

A TCLE, pronounced tickle, is a 3-pin logic element with input A and

> outputs X and Y.
>
> X = A and Y = \A
>
> with perfect symmetry and zero prop delay. I need several on a very
> small board, with 3.3v supply.
>
> TI once made a TTL part, the 74265, with four inside. Actually,
> Digikey will still sell you one. But it's a 5 volt DIP and very slow. >
> I could make one from three XOR gates, one to square up the input edge
> and two to buffer/invert. Available CMOS quad XORS are slow.
>
> I could make it from three NC7SV86P5X tiny xors, which would be pretty
> fast and symmetric and inelegant.
>
> A 1 ns tinylogic flipflop would be great but the truth table is wrong. >
> What's a boy to do?
>

similar to XORs, two LVDS recievers in antiparallel, set one input to ~Vcc/2?

I did something similar with an LT1016 a long time ago. But it may not be fast enough or cheap enough.

Then you need a fast amplifier next to the "pin driver thing".

Driving large fast voltage swings over distance is a very expensive sport.

So you are going to get a reflection at the "pin driver thing" and the "source termination" in the FPGA driver is not going to be good enough to prevent some of that being reflected back into the pin driver.

I do happen to like ECL. LVDS works much the same way.

Certainly. Source terminating an open-ended transmission line causes a doubling of the wavefront at the hi-z load end and a correspondingly giant reflection back into the driver and works great.

The txline will be 75 ohms and the FPGA gives us four choices of drive strength so one should work. A little overshoot at the load end is fine... it overpowers some HF losses.

TinyLogic CMOS parts are as fast as 10K ECL used to be, for a few per cent of the cost and power dissipation. Internally, logic inside an FPGA is far faster than 10EL or 10EP. And maybe 10,000 times cheaper.

My 50-cent DDS frequency systhesizer is clocked at 250 MHz, and uses about 20 milliwatts.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

The question is all about the quality of the source termination. The driver has it own output impedance and that does tend to vary with output voltage.

"Works great" isn't any kind of quantitative assessment.

Varying "drive strength" isn't adjusting the output impedance.In classic CMOS the P-channel transistor had a higher output impedance than the N-channel parts.

That would lead to under shoot at the positive rail and over-shoot at the negative rail.

Presumably the FPGA has four different sizes of transistors, or can couple in more devices if you want a higher current output but that isn't exactly tuning the output impedance.

In any event you are going to have ripple sloshing back and forth along your transmission line, if you can't keep it very short.

Burying the fast stuff in the confined dimensions of a single FPGA mostly evades that problem.

But does it have any high frequency outputs?

We have IBIS simulations of the Trion output drivers, and they look good. We just bought a 1 GHz Rigol scope and its fet probe, so we'll be verifying waveforms soon.

Purchase orders are quantitative.

A bit of over and undershoot is actually good, for shipping logic signals around. It speeds up the critical logic threshold transition.

We're synthesizing an octave, probably 20 to 40 MHz, way below Nyquist, and then dividing down as needed. Limiting it to one octave keeps the passive LC filter simple.

A simple NCO, using the MSB of a phase accumulator, has 4 ns p-p jitter with a 250 MHz clock. That's actually got interesting statistics.

Adding the sine lookup and the dumb DAC and the lowpass filter and comparator reduces the period jitter by at least 20:1.

The math is out of my league so we are designing mostly with simulation and solder.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

and if you use the T version the two will combine to a ~50-60R termination

Thanks, but I'm driving single-ended from an Efinix FPGA so I don't want to end terminate. And I have the hi-Z receivers in stock.

LVDS would have been interesting, but the host PCB is done. This stuff will go on a little baby board, with a 70 ohm ribbon cable.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

single ended source into an input terminated to VCC/2 would basically be similar to Single-Ended HSTL, commonly used for memory

Sure, but source termnated, hi-Z load, would work too. Arguably better, since we'd have twice the swing and twice the slew rate at the receiver. Less power too.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

Nice! DAC R values trial and error?

As it should.The comparator is essentially looking at 4nsec long almost linear ramp between DAC output changes.

Insight could also be useful, if you could achieve it.

Since the source termination has to include the output impedance of the driver which is going to vary with current and output voltage, it's a poorer quality termination.

There's also the catch that if the receiver end rings outside the rails, you can inject current into the receiver integrated circuit substrate, which has been known to have unfortunate side-effects.

Indeed. Can *you* provide us with such insight?

Jeroen Belleman

"Jeroen Belleman" snipped-for-privacy@nospam.please wrote in message news:10tcheg$bniu$ snipped-for-privacy@dont-email.me...

Bill couldn't get below 60dB with over 60 components. The circuit below is comfortably 100dB in simulation with only 18 components.

Version 4.1 SHEET 1 3020 1796 WIRE -176 -208 -288 -208 WIRE 0 -208 -96 -208 WIRE 96 -208 0 -208 WIRE 224 -208 96 -208 WIRE 400 -208 304 -208 WIRE 0 -176 0 -208 WIRE 96 -176 96 -208 WIRE 0 -80 0 -112 WIRE 48 -80 0 -80 WIRE 96 -80 96 -112 WIRE 96 -80 48 -80 WIRE 48 -48 48 -80 WIRE -288 32 -288 -208 WIRE -176 32 -288 32 WIRE -32 32 -96 32 WIRE 48 32 -32 32 WIRE 208 32 128 32 WIRE 256 32 208 32 WIRE 400 32 400 -208 WIRE 400 32 320 32 WIRE 464 32 400 32 WIRE 608 32 544 32 WIRE 656 32 608 32 WIRE 800 32 720 32 WIRE -288 144 -288 32 WIRE -176 144 -288 144 WIRE 208 144 208 32 WIRE 256 144 208 144 WIRE 608 144 608 32 WIRE 656 144 608 144 WIRE -32 160 -32 32 WIRE -32 160 -112 160 WIRE 400 160 400 32 WIRE 400 160 320 160 WIRE 800 160 800 32 WIRE 800 160 720 160 WIRE 832 160 800 160 WIRE 944 160 912 160 WIRE 992 160 944 160 WIRE 1120 160 1072 160 WIRE 1184 160 1120 160 WIRE 1328 160 1264 160 WIRE 1392 160 1328 160 WIRE 1424 160 1392 160 WIRE -176 176 -240 176 WIRE 256 176 224 176 WIRE 656 176 624 176 WIRE 224 208 224 176 WIRE 624 208 624 176 WIRE 944 272 944 160 WIRE 992 272 944 272 WIRE 1120 272 1120 160 WIRE 1120 272 1056 272 WIRE 1184 272 1120 272 WIRE -240 288 -240 176 WIRE -176 288 -240 288 WIRE 400 288 400 160 WIRE 400 288 -96 288 WIRE 1328 288 1328 160 WIRE 1328 288 1248 288 WIRE 1184 304 1120 304 WIRE -240 336 -240 288 WIRE 1120 336 1120 304 WIRE -448 352 -448 320 WIRE -448 352 -496 352 WIRE -496 368 -496 352 WIRE -32 368 -32 160 WIRE 832 368 -32 368 WIRE 944 368 944 272 WIRE 944 368 912 368 WIRE -448 384 -448 352 WIRE -240 448 -240 416 WIRE -288 512 -288 144 WIRE 80 512 -288 512 WIRE 800 512 800 160 WIRE 800 512 160 512 FLAG 224 208 0 FLAG 624 208 0 FLAG -496 368 0 FLAG -448 240 vcc FLAG -448 464 vee FLAG -144 128 vcc FLAG -144 192 vee FLAG 288 128 vcc FLAG 288 192 vee FLAG 688 128 vcc FLAG 688 192 vee FLAG 48 -48 0 FLAG 1216 256 vcc FLAG 1216 320 vee FLAG 1120 336 0 FLAG 1392 160 vout FLAG -240 448 0 SYMBOL res -80 16 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R1 SYMATTR Value 10K SYMBOL res 144 16 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R2 SYMATTR Value 16K SYMBOL res 560 16 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R3 SYMATTR Value 16K SYMBOL cap 320 16 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C1 SYMATTR Value 10n SYMBOL cap 720 16 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C2 SYMATTR Value 10n SYMBOL res 176 496 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R4 SYMATTR Value 10K SYMBOL voltage -448 224 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V3 SYMATTR Value 15 SYMBOL voltage -448 368 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V4 SYMATTR Value 15 SYMBOL OpAmps\\LT1679 -144 160 R0 SYMATTR InstName U5 SYMBOL OpAmps\\LT1679 288 160 R0 SYMATTR InstName U6 SYMBOL OpAmps\\LT1679 688 160 R0 SYMATTR InstName U8 SYMBOL res -80 272 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R8 SYMATTR Value 10k SYMBOL res -256 320 R0 SYMATTR InstName R9 SYMATTR Value 470 SYMBOL diode -16 -176 R0 SYMATTR InstName D1 SYMATTR Value 1N914 SYMBOL diode 80 -112 M180 WINDOW 0 24 64 Left 2 WINDOW 3 24 0 Left 2 SYMATTR InstName D2 SYMATTR Value 1N914 SYMBOL res -80 -224 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R5 SYMATTR Value 47k SYMBOL res 320 -224 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R6 SYMATTR Value 47k SYMBOL res 928 144 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R7 SYMATTR Value 1k SYMBOL res 928 352 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R10 SYMATTR Value 9.1k SYMBOL res 1280 144 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R11 SYMATTR Value 4.7k SYMBOL OpAmps\\LT1679 1216 288 R0 SYMATTR InstName U1 SYMBOL ind 1088 144 R90 WINDOW 0 5 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName L1 SYMATTR Value 68m SYMATTR SpiceLine Ipk=0.05 Rser=90 Rpar=709600 Cpar=15.406p mfg="Würth Elektronik" pn="7447452683 WE-TI 8012" SYMBOL cap 1056 256 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C3 SYMATTR Value 15n TEXT -456 576 Left 2 !.tran 0 10 0 100n startup TEXT -456 632 Left 2 !.options plotwinsize=0 numdgt=15 TEXT -280 -344 Left 2 ;1KHz 100dB based on

And if you replace LT1016 with LT1014 it's still 99dB

Oops LT1679 with LT1014 it's still 99dB

No, they were planned to be R-2R and to get the filter impedance right, but I did tweak R44 to get monotonicity at the MSB transition. That corrects for the roughly 10 ohms source resistance inside the FPGA.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

I thought that reducing the cost of a DDS clock by 40:1 was creative.

We had for decades been buying DDS chips with SPI interfaces. Another virtue of doing the DDS inside a cheap FPGA is frequency-change agility.

Post the schematic of something that you are designing and we can discuss the insight.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics