Re: TCLE

May 03, 2026 Last reply: 5 months ago 41 Replies

And there's only one receiver, right? Otherwise you'll be applying half signal level to some of them until the reflection works it way back, resulting in possible metastability. Source terminated works best with very fast signal edge rates. Does that Tiny Logic drive those low impedances, somewhere in the 100- 300 ohm range, to full VinH,min and VinL,max, or is the receiver not a logic gate?

That so-called elegant solution with the '245 reminds me of the days of MSI logic CPUs with all sorts of multi-phase clock references all over the place, anything of any complexity consumed kilowatts, and the cooling exhaust air was coming out hot enough to burn your hands. The 5V was routed on true bus bars about 1/2 inch thick.

All they did with the 74245 was tap off the conventional TTL phase splitter used to drive a single totempole output, and use it to drive two totempoles, true and complementary. The phase splitter outputs totempole drives were mirror images and in that way achieved theoretical zero skew. Looks like they were after eliminating transmission line common mode reflection with that skew performance, so the market went away with the necessity to drive clock signals tens of feet in distance.

I can try. Insight is in the mind of the beholder, and some ideas are hard to get across, and certainly there were some junior engineers who took a while to get the message.

I got much more comfortable with transformer design after I'd been exposed to the Siemens soft-ferrites application notes, which spelled out the transformer equation. The Mullard Ferrocube application notes had been much less helpful. Other people don't report having the same kind of reaction. Some people do seem to find some ideas hard to get their heads around. There is an Irish expression - if I wanted to get there, I wouldn't have started from here - which may be relevant.

<snipped one more of his LTSpice circuits>

Edward Rawde does seem to be talking about the the very low distortion sine wave oscillator thread. He didn't have much insight into what was going on there, and has been remarkably happy about his own half-baked contributions ever since.

Oh please, not again!

Jeroen Belleman

But scarcely novel.

Analog Devices has been making the chips for decades now. We all know how they work. Setting one up inside a FPGA isn't being all that creative.

History suggests that it wouldn't happen.

Bill Sloman, Sydney

The earliest description I can find for that oscillator (which is the same one JM used) in filter form rather than oscillator form which requires one more resistor is

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58 (pdf page 60) Can anyone trace it back further?

<snipped nonsense>

Very nice! that step correction!

That Rigol DS4034 is a nice scope too, bit expensive..

The original PDP11/20 (I had one of the first ones) was two giant boards full of TTL. It was horrible.

My setup will be

T20 FPGA output pin pcb trace ribbon cable pcb trace two TinyLogic xor gates close together, as my phase splitter

all powered by 3.3 volts. Total length maybe 4 inches.

We'll select an FPGA pin drive strength to about source-terminate 75 ohms. The actual choices (there are four) are a bit under and over 75 ohms, so we'll go under, which will create a bit of overshoot at the xor gates. That will crisp things up.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

Isn't that basically a state-variable filter topology? I am sure goes back earlier than 1978 - I recall seeing it in the 1972 Natsemi LM3900 app note and even then it was not a new topology, I think it was well known in 1960s if not earlier?

piglet

Looks good enough to us. It's just logic. One of my guys will scope it and I can post pics.

Some people just don't like source termination.

The old CD4000A cmos logic would latch up and fry if a signal gently touched the ESD diodes. Modern cmos parts are typically specified to tolerate 50 mA but I've never seen one latch up.

I have seen some mixed-signal parts latch up, like DACs. Maybe a semi process that does good analog is not optimized for logic. Or maybe the superstars at Analog Devices are the analog guys and not much care is given to the digital bits of a chip.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

Certainly someone has done a DDS the way I did it, but I hadn't seen it anywhere.

The fun part was making the DAC out of 5 cents worth of resistors. The comparator threshold servo was fun too.

It's not too late.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

Am 05.05.26 um 20:15 schrieb someone:

This circuit: 2*74LVC04 + 2*100R ser running at 5V (well inside Vabs max)

<
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>

delivers that into a scope, switched to Zin = 50 Ohm:

click to > once or twice.

Sorry for the colors, they look better on the screen than in the screen dump. I'd say: Good enough for 3V3 74LVC input with 50R parallel termination.

Without the series resistors, it's probably OK for 5V CMOS. Just keep the micro strip at 50 Ohm then.

Gerhard

Depends on what you mean.

It’ll overvolt the receiver for one round trip time, because the outgoing amplitude will be more than half the logic swing, and so the initial edge at the receiver will be taller, but it won’t improve the rise time.

You’ll also get pulse top artifacts for a few round trip times. That’s probably not a big worry unless your rep rate is too high. Of course if they get too large, the input diodes will help. (One can diode-terminate ECL.)

Cheers

Phil Hobbs

Yes

I was curious about its origins. The term Bi-Quad also seems to be used. See fig 40

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Under-terminating the driver end will make the receive end amplitude a little bigger, and overshoot a bit. Seems to me that a higher amplitude edge would have a higher slew rate.

I can expect a bit of HF loss from the traces and ribbon cable and the connectors. Overshoot should compensate that some.

I mostly want low jitter and low prop delay. Given a 6" run, I can hardly get that very wrong, especially using the 1 ns XOR gates to split the phases.

Rep rate will be low, 10 MHz maybe, but I do want to ship some narrow pulses, down to 2 ns maybe. 6", round trip twice, is right in the range of reflections mattering.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

did you check the IBIS model?

almost all "modern" CMOS logic explicitly allows 10s of mA injected

old fashion parallel PCI used source termination

Not a ringing endorsement.

It always is, until it misbehaves.

Scoping a working device does exclude the ones that don't work.

It's more difficult to get them absolutely right.

I had precise A/D converter that got a little less precise when the input being digitised got close to the rails. A germanium diode that clipped an in-coming signal to ground before the substrate diodes could catch it solved the problem. Latch-up is a rather more gross failure.

They talked about putting "moats" around sensitive bits of circuitry to prevent charge carriers migrating in from the wrong side of the tracks. Barry Gilbert really did have a stable of impressive experts, and he doesn't seem to have drunk as much as Bob Widlar. I met him once and like him. I doubt if I would have enjoyed a face-to-face encounter with Jim Thompson.

Nor looked hard for an example.

We all know about cheap R:2R DACs. If you use expensive resistors and low resistance switches they can perform pretty well, but you didn't do that.

Not that you've told us why you needed one.

But pretty unlikely.

Bill Sloman, Sydney

Please post a link or two.

I did do some simulation to, among other things, pick the number of resistors, and match them to the lowpass filter design.

Not having a single suitable math tool, I wrote a PowerBasic program to do the digital parts and output a PWL file, and opened that in LT Spice to do the dac+filter+comparator stuff. And then we did a JLC proto board with the FPGA and such.

LT is *terrible* with digital stuff. Qspice looks better.

I used what we have in stock. It works very well.

It should be obvious that the comparator should slice at about the midpoint of the sinewave swing. This does it almost perfectly with two parts.

The LVDS receiver has a bit of deliberate DC offset, but that's small. If you buy a nearly identical part with nominal zero input offset, labeled as a "comparator", it costs over 5x as much.

That's your choice.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

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