Re: TCLE

May 03, 2026 Last reply: 2 months ago 23 Replies
J

Under-terminating the driver end will make the receive end amplitude a little bigger, and overshoot a bit. Seems to me that a higher amplitude edge would have a higher slew rate.

I can expect a bit of HF loss from the traces and ribbon cable and the connectors. Overshoot should compensate that some.

I mostly want low jitter and low prop delay. Given a 6" run, I can hardly get that very wrong, especially using the 1 ns XOR gates to split the phases.

Rep rate will be low, 10 MHz maybe, but I do want to ship some narrow pulses, down to 2 ns maybe. 6", round trip twice, is right in the range of reflections mattering.

John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics

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L

did you check the IBIS model?

almost all "modern" CMOS logic explicitly allows 10s of mA injected

old fashion parallel PCI used source termination

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B

Not a ringing endorsement.

It always is, until it misbehaves.

Scoping a working device does exclude the ones that don't work.

It's more difficult to get them absolutely right.

I had precise A/D converter that got a little less precise when the input being digitised got close to the rails. A germanium diode that clipped an in-coming signal to ground before the substrate diodes could catch it solved the problem. Latch-up is a rather more gross failure.

They talked about putting "moats" around sensitive bits of circuitry to prevent charge carriers migrating in from the wrong side of the tracks. Barry Gilbert really did have a stable of impressive experts, and he doesn't seem to have drunk as much as Bob Widlar. I met him once and like him. I doubt if I would have enjoyed a face-to-face encounter with Jim Thompson.

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