I have a fast 3.3 volt logic level that I'd like to split into inverted and non-inverted copies with minimum time skew.
I think that TI once had a buffer with one input and complementary outputs, but I can't find a reference to that. It's probably slow and obsolete.
A TTL to RS485 converter sort of works but would be slow.
I could use two separate XOR gates, one as a buffer and the other as an inverter. NC7SV86 is a single Tiny Logic 1 ns XOR. Given separate packages and different logic functions, delay symmetry might be suspect.74AUC2G86 is a dual XOR, with < 2ns delay. Fair. I can envision some asymmetry when it inverts vs when it doesn't.
Maybe a Tiny flipflop, like NC7SV74, could be harassed into being a buffer. Q and Qbar may be pretty symmetric.