complementary cmos levels

CMOS parts have different rise and fall times (PMOS half needs more input capacitance to give output conductance than the NMOS half), but a flipflop with the outputs anti-coupled with a small transformer will have matching slew AND impedance, at the highest frequencies of the input waveform. I'm thinking a ferrite bead with two wires.

You'd want to load the outputs symmetrically, of course.

If you had a LVDS or ECL input signal and cared more that the delay from the rising edge at the input to the rising edge at one output is the same as the delay from the falling edge at the input to the rising edge at the other output, then you could use two identical differential to single-ended converters with the input pair of one of them swapped in polarity. It sounds like this isn't what you want though.

The data sheet doesn't address delay symmetry. Tpd from (some input) to (some output) is 1 to 4 ns at 3.3 volts.

I could use an analog ADC driver diffamp, but that's overkill.

Could be done with discretes, ditto.

MC10EL89 has real diff outputs, but swings a bit under 2 volts and needs a lot of power and is expensive.

I worry about ECL going obsolete too.

There are also reasonably quick DIY gates (a modern version of the ancient TTL and-or-invert) such as NC7SZ58P6X. I don't know how symmetrical their delays are, but you have 4 choices of configuration to make an inverter and 4 for a buffer, so you might find two that are close.

Cheers

Phil Hobbs

iptechnology.com:

two of your favorite LVDS recievers, bias on one input to vcc/2 swap inputs on one of them ?

I recently used a 74VHC86 to produce complementary polarities. The data sheet said "balanced propagation delays," but tpd(max) was < my |tpdA-tpdB| target, so I didn't bother actually measuring.

"Balanced propagation delays: tpLH ? tpHL"

Cheers, James Arthur

Interesting, but I hate it whan a claim is made on sheet 1 of a data sheet, and then it's not quantified anywhere.

The specified prop delay over temperatre is 1.0 to 16.5 ns!

That would work. DS90LV012A is our default receiver. It actually has rise and fall prop delay specified separately, with a typ difference of 100 ps, max 400. I'm guessing that a pair of Tiny 1ns XORs (off the same reel) would be about that good.

In one case, my diff signals come from a 1 ns Tiny D-flop with Q and \Q pins, which is probably about as good as I can do. In another case, I need to split an unclocked single-ended signal into differential to drive another gadget.

mandag den 17. februar 2020 kl. 19.34.36 UTC+1 skrev John Larkin:

dsniptechnology.com:

and the companion transmitter is max 700ps, 1.1ns would make the claimed

I don't like it either. But FWIW the claim's existence suggests the designers consciously tried to balance the prop delays.

Yep. LVDS is probably safer. Or PECL for the split, feeding into level translators. Or a transformer.

Cheers, James Arthur