Re: MOSFET Drain-Source Leakage

Hi :

> > I have screwed up and designed a circuit neglecting the Vge=0 value of > drain-source current in an (N-type) MOSFET (it is discharging an integrating > capacitor and the 1 to 10uA makes a few % error which is too much) > > The only kludge I can do at this point is make Vge a few volts negative when > I want the FET off, but I can't find any information on the effect of this > on the leakage current. > > Does anybody know if the drain-source current would be significantly reduced > by a negative gate bias - I have a feeling that since this current is due to > thermally generated carriers, a negative bias might not help. > > Thanks > Gary

You could use a smaller FET as others have suggested (maybe a FST3125 would do or maybe open-drain CMOS logic inverters, or Joerg would know what is available cheaply these days).

You could use two discrete FETs in series, and then when the FETs are both turned off, drive the midpoint between the two FETs through a resistor from a voltage follower that senses and copies the voltage on the node where you want low leakage. The follower could be made from a CMOS opamp (e.g. LMC6041 or another one with less offset voltage would be even better, or you might need a faster one, depending on your circuit). This way, the MOSFET that connects directly to the node where you want low leakage has about zero VDS, and therefore very low leakage. If you want to get really fancy and worry about gate leakage, then you could servo the gate voltage of the top MOSFET to be equal to the high impedance node voltage as well.

View in fixed width font:

Node to be reset -------*--------------. | | D | --G | | S /| | | | /+|----' --* *-RR-*-< | | | | \\-|--. | D | \\| | --G | | S '-------' | GND

Chris

Reply to
chrisgj198
Loading thread data ...

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.