You could use a smaller FET as others have suggested (maybe a FST3125 would do or maybe open-drain CMOS logic inverters, or Joerg would know what is available cheaply these days).
You could use two discrete FETs in series, and then when the FETs are both turned off, drive the midpoint between the two FETs through a resistor from a voltage follower that senses and copies the voltage on the node where you want low leakage. The follower could be made from a CMOS opamp (e.g. LMC6041 or another one with less offset voltage would be even better, or you might need a faster one, depending on your circuit). This way, the MOSFET that connects directly to the node where you want low leakage has about zero VDS, and therefore very low leakage. If you want to get really fancy and worry about gate leakage, then you could servo the gate voltage of the top MOSFET to be equal to the high impedance node voltage as well.
View in fixed width font:
Node to be reset -------*--------------. | | D | --G | | S /| | | | /+|----' --* *-RR-*-< | | | | \\-|--. | D | \\| | --G | | S '-------' | GND
Chris