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Re: Designing a Lumped Delay Line

Can someone point me to information on how to design a lumped delay

>line? > >Thanks! > > ...Jim Thompson

The simple way is just a string of Ls and Cs.

in--------+---L-----+----L----+----L----+---------out | | | | | | | | C/2 C C C/2 | | | | | | | | | | | | gnd gnd gnd gnd

where

Zo = sqrt(L/C)

Fc = 1/(PI * sqrt(LC))

Td = N * sqrt(LC)

There are fancier formulations, like bridged-tees and such, for specific applications. See the Williams filter book.

The nasty part is that the number of sections explodes as (I recall) the square of the delay/risetime ratio. I have a Basic program that does that math and such.

These things ring, too.

John

Reply to
John Larkin
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I have a version that has an R in series with each L. I was just wondering if there is an optimization.

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
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Reply to
Jim Thompson

The simplest solution for a delay line is a Bessel filter. It is obviously not very optimal, however it is canned.

The order of filter is proportional to the bandwidth x delay time.

Yea... Those things are desinged by optimization of the allpass sections, but it is so boring.

Yes. Take FPGA, make 1-bit delta-sigma ADC, then a shift register, then delta-sigma DAC.

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

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Reply to
Vladimir Vassilevsky

On Wed, 23 Apr 2008 21:51:49 -0500, Vladimir Vassilevsky wrote: ...

^^^^^^^^^^^^^^^

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Just FMI (for my information): if it's delta-sigma one way, shouldn't it be sigma-delta the other way? (Of course, I have no clue which should be which.)

Thanks, Rich

Reply to
Rich Grise

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