Re: Crossover Elimination Using the "it won't be easy" Circuit

Real op amps tend to have mismatched and asymmetrical slew rates, which will make life exciting on large transients.

Cheers

Phil Hobbs

Me too. Op amp models are mostly terrible anyway.

You say that like it’s a bad thing. ;)

Cheers

Phil Hobbs (Coming to you from Louis Armstrong International in sunny NOLA, where it’s

20 degrees warmer than at home.)

The semiconductor companies advertise their part in other places. Fouling up a circuit simulation program with ads isn't a great idea.

You can do it for yourself with Firefox or Chrome, which are designed to do that job.

Of course he does. It's not a good idea.

And they won't get any better if people don't use them and complain about their defects. Jim Thompson tried to get manufactures to pay him to set up more realistic models, but his personality may have got in the way.

It's the free market doing exactly what it is supposed to. Admittedly, most of they new parts are me-too versions of other people's parts, but Linear Technology made a business to taking other people's new parts and making them better that the originals.

And AD took Linear Technology's LT1028 and trumped it with the AD797, at a rather higher price.

AD797 is the brainchild of Scott Wurcer @ AD, not of LT. It does not feature the noise peak at 300 KHz like the LT1028, for example.

Funny enough, TI's op amp models seem to work better in LTspice than those from AD or LT. The ADA4898 got nothing right: noise, phase slope... The new model from maybe 2 years ago is somewhat better but still has weird effects if I use more than 1 of them per simulation. I would not know how to invoke that if I wanted.

Gerhard

On Sat, 23 Dec 2023 19:45:51 -0800 (PST), Anthony William Sloman snipped-for-privacy@ieee.org wrote:

Your LTSpice .asc file at

to be badly broken.

You are unlikely to find VBIC models of discretes anywhere, your best bet is running a SGP model through the sgp2vbic perl script and then tweaking. There's a starting point for a 3904 VBIC model (not created or checked by by me) in the attached LTSpice asc listing. I've tried it in a npn version of figure 10 of Mr Baxandall's paper but LTSpice does not handle it properly (I haven't bothered to look to see which VBIC parameters LTSpice supports). It does however work in the Simetrix simulator, and probably will in ngspice. NXP might give you level 50x (Mextram) models under NDA. I seem to recall that they used to give a some examples in their compact model interface simkit, but I downloaded the latest one just now and they seem to have been removed.

Version 4 SHEET 1 2036 1304 WIRE 416 64 288 64 WIRE 480 64 416 64 WIRE 544 64 480 64 WIRE 656 64 544 64 WIRE 416 80 416 64 WIRE 544 96 544 64 WIRE 656 96 656 64 WIRE 416 176 416 160 WIRE 416 176 -16 176 WIRE -16 192 -16 176 WIRE 288 240 288 64 WIRE 416 240 416 176 WIRE 480 240 416 240 WIRE 544 240 544 176 WIRE 656 240 656 160 WIRE 656 240 544 240 WIRE 416 256 416 240 WIRE 480 256 480 240 WIRE 656 272 656 240 WIRE -16 288 -16 272 WIRE 112 288 -16 288 WIRE 224 288 192 288 WIRE 16 336 -16 336 WIRE 64 336 16 336 WIRE 144 336 64 336 WIRE 416 336 416 320 WIRE 480 336 480 320 WIRE 480 336 416 336 WIRE 144 352 144 336 WIRE -16 400 -16 336 WIRE 64 400 64 336 WIRE 144 432 144 416 WIRE 192 432 144 432 WIRE 288 432 288 336 WIRE 288 432 272 432 WIRE 304 432 288 432 WIRE 416 432 416 336 WIRE 416 432 304 432 WIRE 144 464 144 432 WIRE -16 544 -16 480 WIRE 64 544 64 480 WIRE 64 544 -16 544 WIRE 144 544 144 528 WIRE 144 544 64 544 WIRE 304 544 304 432 WIRE 416 544 416 432 WIRE -16 560 -16 544 WIRE 112 592 -16 592 WIRE 240 592 192 592 WIRE -16 608 -16 592 WIRE 384 624 384 608 WIRE -16 704 -16 688 WIRE 416 704 416 624 WIRE 416 704 -16 704 WIRE 416 736 416 704 WIRE 480 736 416 736 WIRE 416 752 416 736 WIRE 480 752 480 736 WIRE 304 832 304 640 WIRE 416 832 416 816 WIRE 416 832 304 832 WIRE 480 832 480 816 WIRE 480 832 416 832 WIRE 480 864 480 832 FLAG 16 336 VL FLAG 480 864 0 FLAG 656 272 0 FLAG -16 560 0 FLAG 480 64 VCC SYMBOL cap 128 352 R0 SYMATTR InstName Ca SYMATTR Value 3n9 SYMBOL cap 128 464 R0 SYMATTR InstName Cb SYMATTR Value 35n2 SYMBOL cap 640 96 R0 SYMATTR InstName C3 SYMATTR Value 25u SYMBOL res 48 384 R0 SYMATTR InstName RL SYMATTR Value 3k SYMBOL ind2 0 384 M0 SYMATTR InstName LT SYMATTR Value 3m56 SYMATTR Type ind SYMATTR SpiceLine Rser=3.56 Cpar=71p2 SYMBOL ind 288 416 R90 WINDOW 0 5 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName LF SYMATTR Value 321u SYMBOL res 208 576 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R2 SYMATTR Value 100 SYMBOL ind2 0 704 R180 WINDOW 0 36 80 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName LB2 SYMATTR Value 40u SYMATTR Type ind SYMATTR SpiceLine Rser=0.4 Cpar=7p2 SYMBOL diode 432 320 R180 WINDOW 0 24 64 Left 2 WINDOW 3 33 93 Left 2 SYMATTR InstName D2 SYMATTR Value 1N4148 SYMBOL cap 464 256 R0 SYMATTR InstName C2 SYMATTR Value 100n SYMBOL res 400 64 R0 WINDOW 3 46 79 Left 2 SYMATTR Value 100k SYMATTR InstName R4 SYMBOL res 96 272 M90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R1 SYMATTR Value 100 SYMBOL ind2 0 288 R180 WINDOW 0 36 80 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName LB1 SYMATTR Value 40u SYMATTR Type ind SYMATTR SpiceLine Rser=0.4 Cpar=7p2 SYMBOL diode 432 816 R180 WINDOW 0 24 64 Left 2 WINDOW 3 28 0 Left 2 SYMATTR InstName D1 SYMATTR Value 1N4148 SYMBOL cap 464 752 R0 SYMATTR InstName C1 SYMATTR Value 100n SYMBOL res 400 528 R0 SYMATTR InstName R3 SYMATTR Value 100k SYMBOL voltage 544 80 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value 14 SYMBOL npn 224 240 R0 SYMATTR InstName Q3 SYMATTR Value 2N3904 SYMBOL npn 240 544 R0 SYMATTR InstName Q4 SYMATTR Value 2N3904 TEXT -48 120 Left 2 !K1 LB1 LB2 LT 0.99 TEXT -48 88 Left 2 !.tran 0 5m 0 TEXT 880 -280 Left 2 !.model Q2N3904L4 npn\n* VBIC model parameters generated from above data by perl script sgp2vbic\n* see

\n+ level=4\n+ rcx =

2.65711\n+ rci = 0.0\n+ rbx = 0.634251\n+ rbi = 5.203349\n+ re = 0.0001\n+ is = 1.26532e-10\n+ nf = 1.5\n+ nr = 2.89609\n+ fc = 0.512134\n+ cje = 4.64214e-12\n+ pe = 0.4\n+ me = 0.256227\n+ cjc = 3.015688e-12\n+ cjep = 7.53922e-13\n+ pc = 0.4\n+ mc = 0.238109\n+ cjcp = 0\n+ ps = 0.75\n+ ms = 0.5\n+ ibei = 6.13333850374693e-13\n+ nei = 1.5\n+ iben = 2.30771e-09\n+ nen = 3.31052\n+ ibci = 6.13333850374693e-12\n+ nci = 2.89609\n+ ibcn = 2.30771e-09\n+ ncn = 1.9876\n+ vef = 566.483710419377\n+ ver = 8.69028854282359\n+ ikf = 0.0272221\n+ ikr = 0.272221\n+ tf = 4.19578e-10\n+ xtf = 0.906167\n+ vtf = 8.75418\n+ itf = 0.0105823\n+ tr = 6.82023e-08\n+ td = 0\n+ ea = 1.05\n+ eaie = 1.05\n+ eaic = 1.05\n+ eane = 1.05\n+ eanc = 1.05\n+ xis = 1\n+ xii = 0.9\n+ xin = 0.668948\n+ kfn = 0\n+ afn = 1\n* avalanche parameters added according to\n* page 13\n* You have to play with both parameters to obtain suitable description of real transistor behaviour!\n* This is just a guess!!\n+ avc1 = 0.02\n+ avc2 = 110 TEXT -40 -128 Left 2 ;An NPN version of Figure 10 from the paper\nTRANSISTOR SINE-WAVE LC OSCILLATORS\nby P.J. BAXANDALL (IEE Paper No. 2978E Feb. 1960)\n \nJM 24/12/23 TEXT -32 936 Left 2 ;The 3904 VBIC model will require tweaking!

It's been up for more than ten years. When I loaded it into LTSpice 17 it did behave oddly, and I had to correct L1 and L2 back to 0.25mH and L3 and L4 back to 22.5uH.

I'll fix it sometime soon.

Around 2005 I asked a member of my Dutch hockey team who worked for NXP in a fairly senior role,and didn't get anywhere.

Snipped the .asc file - I've copied it and will run it in the next day or two, after I've survived Christmas with my younger brother and his five kids and dozen or so grand-kids.

John Larkin's grasp of social dynamics isn't great. A shared distaste for John Larkin's superficial observations isn't any kind of basis for a long term relationship.