"The AVR32 was developed by Atmel's 20-person engineering team in Trondheim, Norway. The team claims the AVR32 achieves 35 percent more throughput per instruction cycle than an ARM11 core when used to run such target algorithms as sum of absolute differences and inverse discrete cosine transforms."
I saw the article in EE Times but nothing about it on Atmel's web site.
AVR32 core. The first, a system-on-chip solution for consumer multimedia applications, is scheduled for introduction in early April.
Atmel's fabs, Atmel says it will not license the core to other vendors. Third parties can have it in a custom chip, but Atmel will insist on building that device.
$17 range, according to the company.
So, we can conclude it is not released off-the-shelf yet. due April. They do NOT mention the merchant uC sector, but target multimedia/ASIC. See the high price. ie Probably this has no on chip FLASH ( too slow ).
It is also very single sourced, but Atmel probably worked out the ARM license fees their foundry customers were paying to ARM, and decided, they would like a slice of that....
It will have to compete with devices like :
Could result in some interesting internal politics between the Atmel ARM devices, and this new, custom 32 bit design.
-jg
On 03/02/2006 the venerable Jim Granville etched in runes:
. . .
the AVR32 core. The
scheduled for
. . .
Ah yes, perhaps April 1st would be a good date. If Atmel's performance on the AVR32 is similar to the Mega256x devices then I wouldn't expect silicon before April 2007 or even
2008.-- John B
In article , John B writes
Apparently people have seen it running
-- \\/\\/\\/\\/\\/\\/\\/\\/\\/\\/\\/\\/\\/\\/\\/\\/\\/\\/\\/\\/\\/\\/\\/\\/\\ \\/\\/\\/\\/\\ Chris Hills Staffs England /\\/\\/\\/\\/ /\\/\\/ chris@phaedsys.org www.phaedsys.org \\/\\/\\ \\/\\/\\/\\/\\/\\/\\/\\/\\/\\/\\/\\/\\/\\/\\/\\/\\/\\/\\/\\/\\/\\/\\/\\/\\/\\/
On 06/02/2006 the venerable Chris Hills etched in runes:
the
even
In the streets of Glasgow people see water running, it usually turns out to be recycled lager. }:-}
-- John B
The big picture of the architecture looks a lot like a variation of the PPro/P II family. I see the instruction stream being fed into a parallel instruction decoder (different details, of course, but similar idea.) This goes into what appears to be something quite like the RISC execution unit also found in the PPro and P II varieties, the re-order buffer for out of order execution, registration units for the functional parts, and a retire unit which retires completed entries in the ROB, posting results to registers in order. This overall theme is nothing new and has been around a long time.
Jon
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