Random Bit Generator

OK. Got it working. Repeats at 255.

What was confusing me was the double-talk about numbering the shift-register stages. Must be Physics majors who still have their direction of current reversed ;-)

Thanks again, David! ...Jim Thompson

Yep, That's a good one. Thanks! ...Jim Thompson

rs,

That's just thinking SMALL. Get an analog TV tuner card, set it to some station that doesn't exist (UHF channel eleventy-three), and record a few gigabytes of static. Discard the high bits of each byte.

A 1-transistor superregen receiver, with no input, makes tons of noise. Interesting circuit.

John

No problem. "Breadboarded" instantly in PSpice ;-)

I'm currently running with taps at 8,4,3,2 and getting a 255-long sequence. ...Jim Thompson

Nah - it's a digital nerd thing - Typically, for a binary output, Q0, Q1, ... Qn, the bit position corresponds to that power of two. As far as which way you shift, there's a holy war between little-endian and big-endian, but ssentially, it's a coin toss. :-)

Cheers! Rich

Do I dare mention Don Lancaster's TTL Cookbook? He's got schematics up to some fairly long length - I don't recall off the top of my head how long, but it's definitely more than 16.

Cheers! Rich

That's there in case some random glitch inserts or removes a bit, accidentally leading to the stuck state.

Cheers! Rich

XOR some of Sloman's messages. ;-)

Aaargh!

Sorry about that...

Normally the counter jumps over the all-zeroes lockup state and runs at a length of 2^n - 1.

The error here (egg on face) was that by forcing the counter into the all-zeroes state, once every cycle, a lot (all?) of the states which would have existed on the other side of the jump are killed off.

The right way, if starting up in (or accidentally falling into) the all zeroes state is a concern, is to NOR all the Q's and feed the NOR output to the XOR, as shown.

That way, the counter runs at maximal length normally, but forces a 1 into the shift register's serial input if its outputs all go to 0, for whatever reason.

The way it was done in old analog synthesizers was to take something like a 2N3904, cut off the collector leg and reverse bias the emitter base junction through a 1 Meg resistor. Capacitor couple to an an opamp with a gain of about 100.

detectors,

Clocked bits? ...Jim Thompson

Just sample the resulting value with 2 or 3 flops in series to reduce metastability and you get your clocked bits. Beware that, obviously, this doesn't give you any reproducibility.

Ken S. Tucker:

No, it was the getting in and out of an Hartmann node.

I like better Wiener bridges. But also Frankfurters are not bad. ;-)

What I have now...

Newsgroups: alt.binaries.schematics.electronic Subject: Random Bit Generator (from SED) - DevelopRandomBits.pdf Date: Fri, 22 Oct 2010 11:20:37 -0700 Message-ID: ...Jim Thompson

So everybody is suggesting the LSFR. LSFRs are trivial; zero state problem has to be dealt with. I try doing something different just for the sake ot it.

Take two binary counters. One counts to 2^N, the other one counts to some odd number. Compute parity function of both counters. Here you go.

Take a binary adder and a register. Add some odd number at every cycle. Tale a bit somewhere from the middle of the register.

Take a binary adder and a register. Multiply by (2^N - 1), i.e. leftshift and subtract. Set the LSB to 1 to avoid all zero state.

There is approximately a zillion of ways of making quazi random (or true random) generator from whatever stuff you got in the drawers. BTW, some

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant