Only in your eyes. You have a grudge against people and you can't see their posts for what they are... at least in this case. *You* are the one trying to start a flame war. Why not just stop?
-- Rick
Due to my inexperience, there are a few points I need to clarify.
The diagram below, previously mentioned, shows Q3 connected to MR. But according to my chart that is the divide by 4 pin. How does this result in divide by 3 at the output?
When you say I can do 4 followed by 2 with one IC, how is that wired?
To derive a divide by 5 and 7, you suggest using separate IC's. From the information at hand, that indicates using Q4 and Q5 respectively. But since Q3 results in divide by 3 (see above) I am now uncertain if these are the correct pins to connect to MR.
And a general question. If I input a 50% duty cycle, does this become increasingly less with progresively higher divide downs? What duty cycle could I expect at divide by 9?
Ken Knowles
Sorry, brain fart. You can do a /3 than a /2 and /3 to get /6 and /9. The others still take separate counters.
Typo, dullard.
Actually, it's JF who is trying to create drama.
You need to look at the data sheet for this part again. The outputs are not divide by 1, 2, 3... This part is a ring counter. One output at a time goes high. If you don't touch the reset pin each output is a divide by 10 with different phases. Only one of the 10 outputs goes high at a time. The web page you found is using the fourth output to reset the counter which means it only outputs pulses on Q0, Q1, Q2, then when Q3 goes high the counter is reset to Q0 being high. There will be a very brief pulse on Q3 in order to make the circuit reset. In this design all of three of the useful outputs are divide by three.
Using this same reset technique with different outputs you can make this chip divide by any number from 2 to 10, but only one output per chip.
I think he mistyped. I think he meant /3 followed by a /2 to give the output a 50/50 duty cycle if that is important.
Connecting Q4 to the reset will give you a divide by 4. To get a divide by 7 connect Q7 to the reset input.
With this chip you will get a 1/9 duty cycle or the output will be high
11.11% of the time.You mentioned filtering the divided clock to get a sine wave, this is not going to work well with waveforms that aren't very square. The harmonic content will be very high to start with. If you use some other devices you can design the NCO type signal generator that others have mentioned which will give you a very close approximation to the sine wave in the first place.
Constructing an NCO will be hard to do using discrete devices, but an FPGA or an MCU would make it much easier. Think of it as a learning opportunity.
-- Rick
As soon as the counter get's to the "fourth" state, it's
*asynchronously" (without a clock) reset to the first state. A complete cycle is then three clocks - Q0, Q1, Q2, Q3 with a reset glitch to Q0. There are only three stable states.If this part had a *synchronous* reset (requires a clock to reset), you would be correct. The states would be Q0, Q1, Q2, Q3, Q0...
Note that this circuit has no "power on" reset, so it could come up in any state, even an illegal one (didn't read the datasheet to see if this was specifically excluded for that part), until the first '1' reaches Q3. This would then reset the counter and only Q0 would be set (valid state-0).
You can't. My mistake. You can do 3 followed by 2 and 3 to get /6 and /9. So you can do both /6 and /9 with five FFs.
You can do any one, but you can't do all simultaneously with one chip.
In this case, 1/9. The input duty cycle doesn't matter, only its period. Each output will be one input clock period in width, no matter what the divide ratio.
Every one should contribute, that's JF's version!
Jamie
yes, exactly. Now where's my Prozac?
Jamie
-- With all the shit that's stored there, I guess a fart every once in a while is inevitable.
In this case JF was not mean nor whiny. Gleen stated obvious Wikepedia copyed stiff, with nothing to do with the problem
Cheers
Klaus
-- Sez you, who - inappropriately - jumps out on the stage in your tawdry way, pretending that your solicitations for attention are, somehow, germane. John Fields
You really need to look at that mirror, JF. It might break, but it'll do you some good.
Bullshit! That's the only reason he posts.
Yep, JF never changes. All you're interested in here is a fight. You are one sad-sack wannabe.
You're nitpicking, simply to show how "smart" you are. You are one sorry individual.
No one expects anything from you, wannabe.
Come on, Keith, knock it off. ...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
Who, Larkin?
-- Rick
-- I realize American English isn't your first language, but viewing one's reflection is accomplished by, as we say, "looking into" or "looking at ones reflection in" a mirror. John Fields
-- Now who's the liar? John Fields
-- Tit for tat.
I agree. Sometimes it pays to look at history and how things escalate from a tit-for-tat exchange and posturing. Sometimes respect is more forthcoming if you don't bite. Perhaps poor old Glene might agree?
Perhaps the most notable escalation are the events after the assassination of a nobody Franz Ferdinand, the consequence of requiring an apology and not getting one, where all were fearful of losing face!
-- Mike Perkins Video Solutions Ltd www.videosolutions.ltd.uk
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.