PSpice Gain/phase model for S/H and quantization in software loop (digital SMPS)

I think you're taking the right approach for the sample & hold and quantization in the transient simulation.

You're almost right with the sampling in the frequency domain -- you're not taking aliasing into account, but as long as your output filter doesn't have appreciable gain above Nyquist then you're all set there.

Traditionally, the way to account for the quantization in the frequency domain is to model it as noise injection. This makes sense if you think about it right: the output of a quantization step is your desired signal plus an error, so you just call that error "noise" and do some analysis.

You would like to be able to model it as being random, which would make it white in the sampled-time domain, and roughly white but perfectly band- limited to the sampling rate in the continuous-time domain. In reality, this only happens if you have enough other noise in the circuit to keep the quantization agitated -- the more pessimistic approach is to model the quantization noise as being a sine wave that is 1.09 a quantization step peak to peak (to account for the fact that it's a square wave), and at the worst possible frequency. This accounts for the fact that -- if all else is quiet -- your circuit will oscillate around a quantization step.

Regardless of whether you assume random or worst-case noise, the way to analyze it is to treat the quantization gain as a signal that's injected at the quantizer, do a sweep to find the transfer function from there to your output, then plug in one of the above two assumptions and see what the noise is on your output.

Shameless plug: this method of treating quantization is covered briefly in my book "Applied Control Theory for Embedded Systems". You'll find it mentioned briefly in chapter 8 (Nonlinear Systems), and in depth in chapter 10 (Software Implications).

If you find that your PWM is too coarse to give good quantization behavior, you may also find this article to be of benefit:

or

Note that you need to pay attention to the output filter bandwidth, and that going to a 2nd-order sigma-delta modulator may be beneficial if you can stand the code complexity.

Yes, that makes sense. Thats what I'm seeing on the scope, it really can never as opposed to an analog controller regulate to the exact target value.

Good insights, thanks :-)

I just may need to buy that book ;-)

My code supports sigma delta, but have not tried it yet, since I want to remove that from the closed loop analysis

Regards

Klaus

you can approximate the phase (time delay) using a pspice transmission line with a delay of 1/2 the sampling period

Mark

The sampling delay in the band of interest could be approximated by allpass filter section. PWM is done with sawtooth waveform and comparator. Quantization error could be modelled by adding noise; however that won't tell about possible limit cycles.

VLV