SMPS feedback loop phase and gain margin

Hi,

What is a good way to increase the stability of a SMPS feedback loop? I have a SMPS that uses this algorithm:

if inductor current > current_limit, pulse off

Duty cycle = ((desired voltage - current voltage) * gain) - (Inductor current * gain2)

I am not sure how to put in the analog or digital adjustments for making sure the feedback loop is stable.

I am reading up on these pages but am not sure how to implement this on a PCB, either analog or in an FPGA:

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cheers, Jamie

Reply to
Jamie Morken
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Sorry..I don't have a direct answer. I'm a newbie in this area. But this post made me think of coming up with a feedback analogy.

I think of feedback like steering a car. With lots of traction, the car responds and turns.

But lets say the road is a little icy....It may take several corrections after making a turn. (Ring)

If icy enough, there might an indefinite amount of course corrections. (Oscillation) (Note: I've yet to oscillate myself home.. :) )

Or one my just go right off the road (latch up).

The phase is related to the timing on when you turn the wheel. The gain is related to how much you turn the wheel.

Not sure if I've made a good analogy but hopefully others will correct me.

Dunno..how the phase margin and gain margin can fit in this analogy. I think it's how much ice it takes to make the car go out of control.

D from BC British Columbia Canada

Reply to
D from BC

You didn't say what sort of DC-DC this is. What you are using as a control equation makes me think it is a simple bucker topology. The equation you have shown won't yeld a very good load regulation.

If this is a design with a continuous inductor current, think of the PWM's signal as having been magically low pass filtered so that you cant see the switching and only see (Duty * Vin)

(Duty * Vin) ----)))))-----+------- Load ! --- ---C1 ! GND

As you can see, from (Duty * Vin) to the load we have a LC filter. If you assume that your equation for doing the control is feeding into a linear system, you have a fairly simple way to make a Bode plot of the system. The issue of the delay in the modulator is not taken into consideration in this plot.

To deal with the modulator, you will usually find that assuming a simple linear delay of 1/2 of a switching cycle will get you into the right ball park.

Basically, you want the duty cycle to be controlled by a PID controller running from the error signal. Your term where you brought the inductor current into the equation is trying to do the "D" part by saying that the current in the inductor tells you the rate of change in the capacitor (C1) voltage.

Using the inductor current in this way doesn't lead to very good performance because you don't get to bring the high frequencies of the load current into the "D" term. This greatly reduces your ability to track a sudden changes in the load.

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Reply to
MooseFET

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