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LT1246 model problems in LT SWcadiii

I've constructed a circuit model showing an LT1246 current-mode PWM regulator that thinks it's regulating a DC output, but isn't.

The AC stability is gratifying, but is not believable while DC characteristics are up the stump.

The whole circuit responds ~ linearly to a varying clamp on the LT1246 'comp' terminal, showing compliance that includes the intended point of regulation.

The feedback circuit will sort of adjust the point of regulation - shunting it gives open loop gain at the primary current limit, controlled at the 'Isense' pin, as is expected.

The impedances attached to the 'FB' pin are all high enough to be handled by the error amplifier's output capabilities, and the feedback pin is a flat line at 2V497 ~ as expected..

I suppose a separate error amplifier added to the model could get around the problem - but the circuit model's credibility suffers.

There were some early issues with the LT1246 model - duty cycles of

100% being one of them. Is anyone aware of other troubles that could account for the DC error amplifier's behavior?

Mr Engelhardt at Linear Tech is on sabatical till early January, so inquiries there are a little difficult.

RL

Reply to
legg
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In article , legg wrote: [...]

(1) The model is no good when the control voltage is below one diode drop.

(2) A few years back, the model or LTSpice made a reference to the overall ground instead of the ground pin of the device. I was working around it and have no idea when they fixed it.

(3) The problem my be your schematic. Look at is very carefully. Grab some of the parts with the dragging hand and make sure that the wires follow them. I've once had a schematic where something looked right but wasn't hooked up.

You could post the schematic since it is text.

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kensmith@rahul.net   forging knowledge
Reply to
Ken Smith

Thanks for the advice. I'm pretty sure now that it's not the fault of the specific model, as I've popped it into other topologies, since, without any trouble. It is intended to function similarly to the 3842 type of current mode controller.

The topology that I was exercising seems to exhibit dynamic reversal, under fixed frequency PWM control. Over short periods, this can give the impression of DC regulation that has become decoupled.

RL

Reply to
legg

It appears that an early asc file had a capacitor typo'd at .01F. Thanks to M.Engelhardt for pointing that out, on his own clock. Check and recheck............ just like a breadboard.

RL

Reply to
legg

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